发布求助
文献互助 智能选刊 最新文献

Proceedings of the Fifth Asian Test Symposium (ATS'96)最新文献

筛选
英文 中文
Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults 两种增强CMOS电路测试生成和桥接故障仿真的建模技术
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555154
Kuen-Jong Lee, Jing-Jou Tang
{"title":"Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults","authors":"Kuen-Jong Lee, Jing-Jou Tang","doi":"10.1109/ATS.1996.555154","DOIUrl":"https://doi.org/10.1109/ATS.1996.555154","url":null,"abstract":"In this paper we present two accurate and efficient modeling techniques for CMOS circuits to enhance the performance of test generation and fault simulation for bridging faults. The first one is a fault modeling technique for inter-gate bridging faults. The second one is an accurate threshold determination method. The accuracy of our model is achieved because all the following factors, including device parameters, voltage operation range of each logic value, resistance of ON-transistors, resistance of bridging faults, and test patterns are considered. The efficiency is achieved due to the simplicity of the solution methods that require no complex circuit level simulation. Experimental data show that SPICE like accuracy can be efficiently achieved.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117244452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
On current testing of Josephson logic circuits using the 4JL gate family 用4JL栅极族测试约瑟夫森逻辑电路的电流
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555158
Teruhiko Yamada, Tsuyoshi Sasaki
{"title":"On current testing of Josephson logic circuits using the 4JL gate family","authors":"Teruhiko Yamada, Tsuyoshi Sasaki","doi":"10.1109/ATS.1996.555158","DOIUrl":"https://doi.org/10.1109/ATS.1996.555158","url":null,"abstract":"This paper discusses limitations of logic testing and capabilities of current testing for logic circuits consisting of the current injection logic gates with four Josephson junctions (4JL gates). We have specified typical fabrication defects of the 4JL gates, and then investigated the voltage and current behavior of defective gates by SPICE simulation to evaluate the defect coverage achieved by logic testing and current testing. The simulation results show that almost half defects cannot be detected by logic testing while more than 90% defect coverage is achievable by monitoring power supply current under multiple test vectors. We have also proposed a current testing scheme for Josephson combinational circuits.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121090395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Invalid state identification for sequential circuit test generation 顺序电路测试生成的无效状态识别
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555128
Hsing-Chung Liang, Chung-Len Lee, Jwu-E Chen
{"title":"Invalid state identification for sequential circuit test generation","authors":"Hsing-Chung Liang, Chung-Len Lee, Jwu-E Chen","doi":"10.1109/ATS.1996.555128","DOIUrl":"https://doi.org/10.1109/ATS.1996.555128","url":null,"abstract":"For sequential circuit test pattern generation, the information on invalid states will help greatly on backward justification to reduce the test generation time. This paper proposes three algorithms to find invalid states for sequential circuit test generation. The first two algorithms search the complete set of invalid states by exploring all valid states and reachable states respectively. The first algorithm is efficient for circuits having more invalid states than valid states while the second algorithm is efficient for circuits having more valid states than invalid states. The third algorithm searches only the invalid states that are required for test generation to stop justification early. Experimental results on ISCAS benchmark circuits show that the algorithm can identify invalid states in short time and can help improve test generation significantly in the fault coverage, detection efficiency, and generation time.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126719005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
DP-BIST: a built-in self-test for DSP data paths-a low overhead and high fault coverage technique DP-BIST:内置的DSP数据路径自检-低开销和高故障覆盖率技术
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555160
S. Adham, Sanjay Gupta
{"title":"DP-BIST: a built-in self-test for DSP data paths-a low overhead and high fault coverage technique","authors":"S. Adham, Sanjay Gupta","doi":"10.1109/ATS.1996.555160","DOIUrl":"https://doi.org/10.1109/ATS.1996.555160","url":null,"abstract":"A new Built-In Self Test (BIST) technique suitable for high performance DSP datapaths is presented. The BIST session is controlled via hardware without the need for a separate test pattern generation register or test program storage. Furthermore, the BIST scenario is appropriately set-up so as to also test the register file as well as the shift and truncation logic in the datapath. The use of DP-BIST enables a very high speed test (one test vector is applied per clock cycle) with no performance degradation and little area overhead for the hardware test control. Comparison between DP-BIST and scan based BIST technique is also presented. We show how DB-BIST can be used a centralized test resource to test other macros on the chip and the integration of DP-BIST with internal scan and boundary scan is addressed.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116721396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An efficient compact test generator for I/sub DDQ/ testing 一个高效紧凑的测试发生器，用于I/sub DDQ/测试
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555156
H. Kondo, K. Cheng
{"title":"An efficient compact test generator for I/sub DDQ/ testing","authors":"H. Kondo, K. Cheng","doi":"10.1109/ATS.1996.555156","DOIUrl":"https://doi.org/10.1109/ATS.1996.555156","url":null,"abstract":"We present an algorithm for generating compact test sets for I/sub DDQ/ testing. The faults considered are: (1) the bridging faults (BFs) between gates and (2) the leakage faults (LFs) within a gate. For the LFs within a gate, we propose a fault model called the Input Fault model (IF). The advantages of the IF model include: (1) it is independent of the physical implementation of the logic design, (2) it guarantees the detection of all internal LFs for any implementation, and (3) the total number of faults is relatively small. We utilize the detectability to guide target fault selection during test generation which leads to a compact set of final patterns. We extend the essential fault (ESF) concept and use it for evaluating the detectability of each fault implicitly. The experimental results show that the size of test set generated based on the proposed method is smaller than those obtained by previously proposed procedures.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128978524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Syndrome simulation and syndrome test for unscanned interconnects 未扫描互连的证候模拟和证候测试
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555138
C. Su, Shyh-Shen Hwang, S. Jou, Y. Ting
{"title":"Syndrome simulation and syndrome test for unscanned interconnects","authors":"C. Su, Shyh-Shen Hwang, S. Jou, Y. Ting","doi":"10.1109/ATS.1996.555138","DOIUrl":"https://doi.org/10.1109/ATS.1996.555138","url":null,"abstract":"In this paper, we present a syndrome test methodology for the testing of unscanned interconnects in a boundary scan environment. Mathematical equations are derived for the relationship of test length, fault-free and faulty syndromes, and tolerable error rate. To calculate fault-free and faulty syndromes, we propose an event driven syndrome simulation algorithm. To shorten testing time and reduce test cost, we transform and solve the problem as a set covering problem.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124959976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A design for testability method using RTL partitioning 设计一种使用RTL分区的可测试性方法
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555142
Toshinori Hosokawa, K. Kawaguchi, M. Ohta, M. Muraoka
{"title":"A design for testability method using RTL partitioning","authors":"Toshinori Hosokawa, K. Kawaguchi, M. Ohta, M. Muraoka","doi":"10.1109/ATS.1996.555142","DOIUrl":"https://doi.org/10.1109/ATS.1996.555142","url":null,"abstract":"We will present a Design For Testability (DFT) method on Register Transfer Level (RTL). In our method RTL circuits are partitioned into some testable blocks, and each of the blocks is isolated by using primary pins and additional multiplexers so that automatic test pattern generation (ATPG) can be applied for each of the blocks. The experimental results for some RTL circuits designed with Bchart show that our method reduces the number of test patterns from a seventeenth to an eightieth and 10 to 30% of area overhead for test circuits in comparison with a full scan design method.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"3 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113975872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Comparison diagnosis in large multiprocessor systems 大型多处理机系统的比较诊断
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555166
C. Fuhrman, H. Nussbaumer
{"title":"Comparison diagnosis in large multiprocessor systems","authors":"C. Fuhrman, H. Nussbaumer","doi":"10.1109/ATS.1996.555166","DOIUrl":"https://doi.org/10.1109/ATS.1996.555166","url":null,"abstract":"We present the bounded symmetric comparison (BSC) model for comparison-based system-level diagnosis. It is based on the symmetric comparison model of Chwa and Hakimi but includes a limit on the number of PEs that can produce identical, faulty results that are used in the syndrome of the diagnosis. We contribute a theorem with necessary and sufficient conditions for one-step diagnosability of a system under the BSC model. We show that previous characterizations for one-step diagnosability under the symmetric (Chwa/Hakimi) and asymmetric (Malek) comparison models are in fact special-case characterizations for the BSC model.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122339672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Circuit partitioned automatic test pattern generation constrained by three-state buses and restrictors 受三态总线和限流器约束的电路分段自动测试模式生成
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555132
J. V. D. Linden, M. Konijnenburg, A. V. Goor
{"title":"Circuit partitioned automatic test pattern generation constrained by three-state buses and restrictors","authors":"J. V. D. Linden, M. Konijnenburg, A. V. Goor","doi":"10.1109/ATS.1996.555132","DOIUrl":"https://doi.org/10.1109/ATS.1996.555132","url":null,"abstract":"Circuit partitioned approaches to ATPG have been developed and used over the last two decades, depending on the ratio between state-of-the-art in ATPG and circuit sizes. A practical form consists of coarse-grain, cone-oriented partitioning of the circuit. We investigated the problems introduced by practical ATPG constraints: keeping tests (3-state) bus-conflict free, and complying to external restrictions and exclusions on test patterns. A cone-oriented circuit partitioning method dealing with these problems is proposed. A serial ATPG scheme for the partitions is proposed. The combined effectiveness is shown by experimental results.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121800376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new scheme for the fault diagnosis of multiprocessor systems 一种多处理机系统故障诊断的新方案
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555173
Xiaofan Yang, Tinghuai Chen, Zehan Cao, Zhongshi He, H. Cao
{"title":"A new scheme for the fault diagnosis of multiprocessor systems","authors":"Xiaofan Yang, Tinghuai Chen, Zehan Cao, Zhongshi He, H. Cao","doi":"10.1109/ATS.1996.555173","DOIUrl":"https://doi.org/10.1109/ATS.1996.555173","url":null,"abstract":"The present paper is concerned with the system-level probabilistic diagnosis problem of multiprocessor systems. First, a new diagnosis algorithm, known as the K-Step-Voting (K-SV) algorithm, is presented. This algorithm generalizes the Majority-Voting (MV) algorithm due to Blough et al. (1992). Then K-SV algorithm is theoretically proved to be better than the MV algorithm. Finally, through computer simulations, the K-SV algorithm is shown to be much superior to the MV algorithm when run on hypercube systems.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123854274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信