On current testing of Josephson logic circuits using the 4JL gate family

Abstract

This paper discusses limitations of logic testing and capabilities of current testing for logic circuits consisting of the current injection logic gates with four Josephson junctions (4JL gates). We have specified typical fabrication defects of the 4JL gates, and then investigated the voltage and current behavior of defective gates by SPICE simulation to evaluate the defect coverage achieved by logic testing and current testing. The simulation results show that almost half defects cannot be detected by logic testing while more than 90% defect coverage is achievable by monitoring power supply current under multiple test vectors. We have also proposed a current testing scheme for Josephson combinational circuits.