Circuit partitioned automatic test pattern generation constrained by three-state buses and restrictors

Abstract

Circuit partitioned approaches to ATPG have been developed and used over the last two decades, depending on the ratio between state-of-the-art in ATPG and circuit sizes. A practical form consists of coarse-grain, cone-oriented partitioning of the circuit. We investigated the problems introduced by practical ATPG constraints: keeping tests (3-state) bus-conflict free, and complying to external restrictions and exclusions on test patterns. A cone-oriented circuit partitioning method dealing with these problems is proposed. A serial ATPG scheme for the partitions is proposed. The combined effectiveness is shown by experimental results.