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Proceedings of the Fifth Asian Test Symposium (ATS'96)最新文献

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An approach to the synthesis of synchronizable finite state machines with partial scan 具有部分扫描的可同步有限状态机的综合方法
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555149
Tomoo Inoue, T. Masuzawa, H. Youra, H. Fujiwara
{"title":"An approach to the synthesis of synchronizable finite state machines with partial scan","authors":"Tomoo Inoue, T. Masuzawa, H. Youra, H. Fujiwara","doi":"10.1109/ATS.1996.555149","DOIUrl":"https://doi.org/10.1109/ATS.1996.555149","url":null,"abstract":"Initialization of sequential circuits is one of time-consuming processes in test generation for sequential circuits, and hence synthesizing sequential circuits of which synchronizing sequences are short is an important approach to reducing the cost of test generation for the circuits. In this paper, we propose an approach to the synthesis of finite state machines (FSMs) with partial scan. We focus on repeating partial scan for synchronizing FSMs, and present an extended synchronizing sequence which consists of scan inputs and normal inputs, and which takes a circuit to a single specific state, regardless of the initial state. To synthesize synchronizable FSMs, we formulate a problem of minimizing extended synchronizing sequence length, and present a heuristic algorithm for the problem. We show the experimental results of the minimization of extended synchronizing sequence length on MCNC'91 benchmark FSMs. The experimental results show that the proposed heuristic algorithm can find a minimum-length extended synchronizing sequence for most of MCNC'91 benchmark FSMs, and the length of the extended synchronizing sequence is three or less for all the benchmark FSMs.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114646694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new model with time constraints for conformance testing of communication protocols 基于时间约束的通信协议一致性测试新模型
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555170
Daisuke Teratani, Y. Kakuda, T. Kikuno
{"title":"A new model with time constraints for conformance testing of communication protocols","authors":"Daisuke Teratani, Y. Kakuda, T. Kikuno","doi":"10.1109/ATS.1996.555170","DOIUrl":"https://doi.org/10.1109/ATS.1996.555170","url":null,"abstract":"In this paper we propose a new model for conformance testing of real-time protocols. First, we point out necessary properties for the model with respect to the following attributes: (1) the description and testing of the time constraints, (2) time-out processing. Although communicating finite state machine (CFSM) and its extension TCFSM are widely accepted as models for communication protocols, these models do not satisfy the necessary conditions, and are not suitable for testing real-time properties. Then we propose a new model CFSM-T which defines a new time constraint [l,u,d] to resolve time difference between clock (logical time) and timer (physical time) and changes the scope of description to processes only. Finally, we apply it to specify the alternating bit protocol. The result shows that the new model CFSM-T would be an effective model of real-time protocols for protocol conformance testing.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123703041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Waveform polynomial manipulation using BDDs 使用bdd的波形多项式操作
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555150
Zhuxing Zhao, Zhongcheng Li, Y. Min
{"title":"Waveform polynomial manipulation using BDDs","authors":"Zhuxing Zhao, Zhongcheng Li, Y. Min","doi":"10.1109/ATS.1996.555150","DOIUrl":"https://doi.org/10.1109/ATS.1996.555150","url":null,"abstract":"A waveform polynomial for a digital circuit integrates both logic and timing information. It is applicable to design verification and test. This paper introduces a compact and manageable form, BPBDD, to represent and manipulate Boolean process based on BDDs, and shows how to construct a BPBDD representing a waveform polynomial for a given circuit. Experimental results show that BPBDD is capable of handling circuits of middle size efficiently. Although it is more complicated than OBDDs, more information about a circuit is available.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125787381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An MISR computation algorithm for fast signature simulation 一种用于快速签名仿真的MISR计算算法
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555161
Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
{"title":"An MISR computation algorithm for fast signature simulation","authors":"Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu","doi":"10.1109/ATS.1996.555161","DOIUrl":"https://doi.org/10.1109/ATS.1996.555161","url":null,"abstract":"A fast multiple input signature register (MISR) computation algorithm for signature simulation is proposed. Based on the linear compaction algorithm, the modularity property of a single input signature register (SISR), and the sparsity of the error-domain input, some new accelerating schemes-partial input look-up tables and reverse zero-checking policy-are developed to boost the signature computation speed. Mathematical analysis and simulation results show that this algorithm has an order of magnitude speedup without extra memory requirement compared with the linear compaction algorithm. Though originally derived for SISR, this algorithm is applicable to MISR by a simple conversion procedure or a bit-adjusting scheme with little effort. Consequently, a very fast MISR signature simulation can be achieved.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129550594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Testable design and testing of MCMs based on multifrequency scan 基于多频扫描的mcm测试设计与测试
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555140
W. Tseng, Kuochen Wang
{"title":"Testable design and testing of MCMs based on multifrequency scan","authors":"W. Tseng, Kuochen Wang","doi":"10.1109/ATS.1996.555140","DOIUrl":"https://doi.org/10.1109/ATS.1996.555140","url":null,"abstract":"In this paper, we present a novel and efficient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method and the smart substrate to provide two levels at speed test. The IEEE 1149.1 boundary scan standard is used to offer the necessity of controllability and observability. Part of the boundary scan cells used in the chip level are modified to form the module level scan chain. Using the chip level boundary scan cells to provide both chip and module level testings, it not only decreases area overhead but also reduces extra delay introduced by the addition of test circuits. The contribution of this paper is to provide an MCM design for testability strategy which has the capability to detect performance defects as well as static faults with small delay and low overhead.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122323695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient multifrequency analysis of fault diagnosis in analog circuits based on large change sensitivity computation 基于大变化灵敏度计算的模拟电路故障诊断多频分析
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555164
Tao Wei, M. Wong, Yim-Shu Lee
{"title":"Efficient multifrequency analysis of fault diagnosis in analog circuits based on large change sensitivity computation","authors":"Tao Wei, M. Wong, Yim-Shu Lee","doi":"10.1109/ATS.1996.555164","DOIUrl":"https://doi.org/10.1109/ATS.1996.555164","url":null,"abstract":"In this paper we present a method for the optimal selection of test points and the generation of test frequencies. Our method is based on large change sensitivity analysis with element level analysis operating in the frequency domain. The fact that the deviation of individual components can be set to arbitrary value ranging from zero to infinity high fault coverage and enhancement in the overall circuit testability are ensured. The proposed method can diagnose both catastrophic and parametric faults. Our results show that both single and multiple faults can be located within small to medium size circuits. The computation is realized by combining the evaluation before test with a symbolic math package. This combination provides low computational cost and proves to be efficient comparing to conventional fault diagnosis methods.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133789065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Test generation of analog switched-current circuits 模拟开关电流电路的测试生成
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555171
Cheng-Ping Wang, C. Wey
{"title":"Test generation of analog switched-current circuits","authors":"Cheng-Ping Wang, C. Wey","doi":"10.1109/ATS.1996.555171","DOIUrl":"https://doi.org/10.1109/ATS.1996.555171","url":null,"abstract":"Based on possible defects on the layout of a practical non-ideal switch, fault model and test generation of current copiers, basic building block of switched-current circuits, are presented in this study. We consider two types of switches, current switches and voltage switches, which have been commonly used in both switched-current circuits and switched-capacitor circuits, and both catastrophic and non-catastrophic faults of transistors used as switches. The generated test sequence achieve full testability of current copiers. The tester and test process are readily applied for any switched-current circuits.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"os-22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130311738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Thermal monitoring of safety-critical integrated systems 安全关键集成系统的热监测
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555172
V. Székely, M. Rencz, J. Karam, M. Lubaszewski, B. Courtois
{"title":"Thermal monitoring of safety-critical integrated systems","authors":"V. Székely, M. Rencz, J. Karam, M. Lubaszewski, B. Courtois","doi":"10.1109/ATS.1996.555172","DOIUrl":"https://doi.org/10.1109/ATS.1996.555172","url":null,"abstract":"On-line temperature monitoring of safety-critical ICs and systems becomes more and more crucial because of downsizing of integrated circuits and of increased density due to advanced packaging. To prevent erroneous operation, temperature sensors should be placed on the critical spots, the outputs of which should be read by means of boundary scanned architectures or modified boundary scanned architectures in case of on-line monitoring.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129055274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A consistent scan design system for large-scale ASICs 一种用于大规模集成电路的一致扫描设计系统
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555141
Y. Konno, Kazushi Nakamura, T. Bitoh, K. Saga, S. Yano
{"title":"A consistent scan design system for large-scale ASICs","authors":"Y. Konno, Kazushi Nakamura, T. Bitoh, K. Saga, S. Yano","doi":"10.1109/ATS.1996.555141","DOIUrl":"https://doi.org/10.1109/ATS.1996.555141","url":null,"abstract":"Scan design has been widely used as a design-for-testability technique. Its application to large-scale ASICs, however, has been limited because of its insufficient design support system, which causes large hardware overhead resulting in lower routability. To overcome these problems, we developed a consistent scan design system that automatically networks scan elements in a circuit, improves routability by rechaining scan elements, and verifies scan operation. The system enables us to design ASICs with a scan path in a shorter design period than LSIs without a scan path, because functional test patterns do not need to be generated. Using the system, we developed over one hundred ASICs with up to 340000 gates, and obtained test patterns with a fault coverage of more than 95%. The design data shows that the scan-path wiring is reduced to 15.7% of the conventional design and the delay compensation gates are reduced to 3.9% of the conventional design. The total circuit overhead of an ASIC containing more than one million transistors is reduced from 12.6% to 5.0% by using this design system.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125045338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An efficient PRPG strategy by utilizing essential faults 利用基本故障的有效PRPG策略
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555159
L. Huang, Jing-Yang Jou, S. Kuo
{"title":"An efficient PRPG strategy by utilizing essential faults","authors":"L. Huang, Jing-Yang Jou, S. Kuo","doi":"10.1109/ATS.1996.555159","DOIUrl":"https://doi.org/10.1109/ATS.1996.555159","url":null,"abstract":"One major drawback of the LFSR-based BIST is its low fault coverage. To obtain the complete fault coverage, multiple seeds and multiple polynomials are usually required. One way to find the seeds and polynomials for the LFSR was utilizing the Gauss-elimination procedure. In this approach, the test patterns which are generated by LFSR are modeled as a set of multivariable linear equations. It is created from a given deterministic test set. The corresponding seed and polynomial are then obtained from the solution of this equations set. However, given the original deterministic test set without don't cares, it were not acceptable on the random pattern resistant circuits. In this paper, we allow the test patterns to have don't care values. With an intelligent heuristic of further utilizing the essential faults, this approach becomes much more efficient even for the random pattern resistant circuits. The experimental results on the ISCAS-85 and the ISCAS-89 benchmarks show that a significant improvement can be obtained both on the hardware overhead and the test length.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125061583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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