A consistent scan design system for large-scale ASICs

Scan design has been widely used as a design-for-testability technique. Its application to large-scale ASICs, however, has been limited because of its insufficient design support system, which causes large hardware overhead resulting in lower routability. To overcome these problems, we developed a consistent scan design system that automatically networks scan elements in a circuit, improves routability by rechaining scan elements, and verifies scan operation. The system enables us to design ASICs with a scan path in a shorter design period than LSIs without a scan path, because functional test patterns do not need to be generated. Using the system, we developed over one hundred ASICs with up to 340000 gates, and obtained test patterns with a fault coverage of more than 95%. The design data shows that the scan-path wiring is reduced to 15.7% of the conventional design and the delay compensation gates are reduced to 3.9% of the conventional design. The total circuit overhead of an ASIC containing more than one million transistors is reduced from 12.6% to 5.0% by using this design system.