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Proceedings of the Fifth Asian Test Symposium (ATS'96)最新文献

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Realistic linked memory cell array faults 现实链接存储单元阵列故障
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555157
A. V. Goor, G. Gaydadjiev
{"title":"Realistic linked memory cell array faults","authors":"A. V. Goor, G. Gaydadjiev","doi":"10.1109/ATS.1996.555157","DOIUrl":"https://doi.org/10.1109/ATS.1996.555157","url":null,"abstract":"The problem of designing memory tests is to establish a relevant set of fault models only consisting of those faults which are shown to be possible to occur in practice. Thereafter, it is a challenge to the test designer to design an optimum test covering the faults of the established fault models. A new fault model, the disturb fault model, is introduced. The notation of linked faults is established and it is shown that march tests can only detect a subset of all linked faults. Thereafter, the universe of linked faults is reduced to the set of realistic linked faults. Last, the effectiveness of the realistic linked fault model is shown via new tests with a higher fault coverage and a shorter test length.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115092793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hierarchical testing using the IEEE Std 1149.5 module test and maintenance slave interface module 分层测试使用IEEE标准1149.5模块测试和维护从接口模块
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555136
Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu
{"title":"Hierarchical testing using the IEEE Std 1149.5 module test and maintenance slave interface module","authors":"Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu","doi":"10.1109/ATS.1996.555136","DOIUrl":"https://doi.org/10.1109/ATS.1996.555136","url":null,"abstract":"An IEEE Std 1149.5 MTM-Bus Slave interface module is presented, which is used for direct access to 1149.1 chip-level buses and hierarchical test. All the standard 1149.1 functions, such as SAMPLE/PRELOAD, EXTEST, BYPASS, and even RUNBIST, can be performed within three 1149.5 Read/Write-Data message cycles. The messages are transmitted between the MTM-bus Master module (M-module) and the Slave module (S-module). We adopt the Full TAP Control (FTC) method to activate the 1149.1 Boundary-Scan paths via the 1149.5 MTM-Bus. A personal computer is used as the M-module.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114088106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A test methodology for interconnect structures of LUT-based FPGAs 基于lut的fpga互连结构的测试方法
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555139
H. Michinishi, T. Yokohira, T. Okamoto, Tomoo Inoue, H. Fujiwara
{"title":"A test methodology for interconnect structures of LUT-based FPGAs","authors":"H. Michinishi, T. Yokohira, T. Okamoto, Tomoo Inoue, H. Fujiwara","doi":"10.1109/ATS.1996.555139","DOIUrl":"https://doi.org/10.1109/ATS.1996.555139","url":null,"abstract":"In this paper we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validness and complexity.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126230017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 83
Concurrent error detection and fault location in a fast ATM switch 快速ATM交换机并发错误检测与故障定位
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555146
Yoon-Hwa Choi, Pong-Gyou Lee
{"title":"Concurrent error detection and fault location in a fast ATM switch","authors":"Yoon-Hwa Choi, Pong-Gyou Lee","doi":"10.1109/ATS.1996.555146","DOIUrl":"https://doi.org/10.1109/ATS.1996.555146","url":null,"abstract":"In this paper, we present a concurrent error detection and fault location technique for a fast ATM switch. The switch architecture has multiple data and control planes, each of which has an identical banyan topology. Cell headers are routed via the control planes to reserve their routing paths on the data planes. Multiplicity of data planes for enhancing performance is utilized to detect errors and locate faults during normal operation. An efficient algorithm is developed to locate faulty links or switching elements while normal switching operations are being performed. The identified faulty data planes can also be made usable for cell transmission.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127003897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-complexity fault diagnosis under the multiple observation time testing approach 多观测时间测试下的低复杂度故障诊断方法
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555163
I. Pomeranz, S. Reddy
{"title":"Low-complexity fault diagnosis under the multiple observation time testing approach","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.1996.555163","DOIUrl":"https://doi.org/10.1109/ATS.1996.555163","url":null,"abstract":"The advantages of the multiple observation time approach for fault diagnosis have been demonstrated before by a fault diagnosis procedure based on partial specification of initial states. It was also shown that it is possible to perform fault simulation under the multiple observation time approach at very low computational overhead compared to conventional simulation. In this work, we combine these procedures and propose a low-complexity fault diagnosis procedure under the multiple observation time approach. Several observations made in this work allow us to increase the effectiveness of the proposed diagnosis scheme in terms of the resolution it achieves and its complexity.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127100189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testing and diagnosis of board interconnects in microprocessor-based systems 基于微处理器的系统中电路板互连的测试与诊断
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555137
P. Hsu, Sying-Jyan Wang
{"title":"Testing and diagnosis of board interconnects in microprocessor-based systems","authors":"P. Hsu, Sying-Jyan Wang","doi":"10.1109/ATS.1996.555137","DOIUrl":"https://doi.org/10.1109/ATS.1996.555137","url":null,"abstract":"In this paper we propose a low-cost board-level testing method for printed circuit boards in microprocessor-based systems. The fault detection is achieved by replacing the CPU with a bus emulator to test faults on wiring interconnects. Test patterns are sent by the bus emulator and the results are collected by it later for analysis. We also discuss how to derive minimum test sets for the diagnosis of all modeled faults. Multiple-board systems can be tested by hierarchically applying our method. With this approach, board testing is conducted in a way similar to functional testing while at the same time reach the controllability and observability offered by in-circuit testing.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128588381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults 结合自动测试图生成和内置中间电压检测来检测CMOS桥接故障
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555144
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai
{"title":"Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults","authors":"Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai","doi":"10.1109/ATS.1996.555144","DOIUrl":"https://doi.org/10.1109/ATS.1996.555144","url":null,"abstract":"This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intermediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121659921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Algorithmic test generation for supply current testing of TTL combinational circuits TTL组合电路供电电流测试算法的生成
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555155
T. Kuchii, M. Hashizume, T. Tamesada
{"title":"Algorithmic test generation for supply current testing of TTL combinational circuits","authors":"T. Kuchii, M. Hashizume, T. Tamesada","doi":"10.1109/ATS.1996.555155","DOIUrl":"https://doi.org/10.1109/ATS.1996.555155","url":null,"abstract":"In this paper, an algorithmic test generation method for supply current testing of TTL combinational circuits is proposed. In this method, primary input assignment like in PODEM is used for sensitizing a fault and generating the fault effect on supply current of a circuit under test. Test input vectors for ISCAS-85 benchmark circuits are derived by a random method and the proposed algorithmic method. The test generation results show that with the algorithmic method, test input vectors of faults, whose test vectors can not be derived with the random method, can be derived.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131719158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On test generation for interconnected finite-state machines-the input sequence propagation problem 互联有限状态机的测试生成——输入序列传播问题
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555129
I. Pomeranz, S. Reddy
{"title":"On test generation for interconnected finite-state machines-the input sequence propagation problem","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.1996.555129","DOIUrl":"https://doi.org/10.1109/ATS.1996.555129","url":null,"abstract":"Test generation for synchronous sequential circuits can be facilitated by decomposing the circuit into a cycle free interconnection of submachines such that all feedback loops are included within the submachines. We consider a test generation procedure that takes advantage of such a decomposition. The paper focuses on one of the subproblems of the test generation problem, the input sequence propagation problem. The problem occurs when a test sequence T is applied to an embedded machine M'. The fault effects of the target faults of M' appear on the outputs of M' and must be propagated through a machine M driven by M'. We propose a solution to the problem of propagating the fault effects of a machine M' through another machine M. The solution maximizes the number of faults whose fault effects are propagated simultaneously. In this way, the overall test generation time and the test application time are minimized.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132459450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Minimal delay test sets for unate gate networks 单栅极网络最小延迟测试集
Proceedings of the Fifth Asian Test Symposium (ATS'96) Pub Date : 1996-11-20 DOI: 10.1109/ATS.1996.555153
U. Sparmann, H. Mueller, S. Reddy
{"title":"Minimal delay test sets for unate gate networks","authors":"U. Sparmann, H. Mueller, S. Reddy","doi":"10.1109/ATS.1996.555153","DOIUrl":"https://doi.org/10.1109/ATS.1996.555153","url":null,"abstract":"We consider delay testing of a specific class of logic circuits, the so called 'unate gate networks (UGNs)', which are of importance for the realization of dynamic CMOS logic and in the field of on-line error detection. It has been shown earlier, that UGNs can be tested completely for delay faults with 'universal' test sets. This result even holds for designs which are not completely path delay testable, since the above test sets check the temporal correctness of a circuit by testing 'path systems' instead of single paths. A universal test set only depends on the computed function and thus, is valid for any unate gate network implementation of this function. This universal test property has to be paid by an increase in test set size, since a design independent test set will in general be larger than a design dependent one. In this paper, we show how to tailor a universal test set to a specific design in order to reduce its size maximally without losing test quality. Experimental results demonstrate that the resulting delay test sets are very compact, and large savings in test set size of up to 96.71% can be achieved compared to the universal test set.","PeriodicalId":215252,"journal":{"name":"Proceedings of the Fifth Asian Test Symposium (ATS'96)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128698802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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