On test generation for interconnected finite-state machines-the input sequence propagation problem

Abstract

Test generation for synchronous sequential circuits can be facilitated by decomposing the circuit into a cycle free interconnection of submachines such that all feedback loops are included within the submachines. We consider a test generation procedure that takes advantage of such a decomposition. The paper focuses on one of the subproblems of the test generation problem, the input sequence propagation problem. The problem occurs when a test sequence T is applied to an embedded machine M'. The fault effects of the target faults of M' appear on the outputs of M' and must be propagated through a machine M driven by M'. We propose a solution to the problem of propagating the fault effects of a machine M' through another machine M. The solution maximizes the number of faults whose fault effects are propagated simultaneously. In this way, the overall test generation time and the test application time are minimized.