Algorithmic test generation for supply current testing of TTL combinational circuits

Abstract

In this paper, an algorithmic test generation method for supply current testing of TTL combinational circuits is proposed. In this method, primary input assignment like in PODEM is used for sensitizing a fault and generating the fault effect on supply current of a circuit under test. Test input vectors for ISCAS-85 benchmark circuits are derived by a random method and the proposed algorithmic method. The test generation results show that with the algorithmic method, test input vectors of faults, whose test vectors can not be derived with the random method, can be derived.