Minimal delay test sets for unate gate networks

Abstract

We consider delay testing of a specific class of logic circuits, the so called 'unate gate networks (UGNs)', which are of importance for the realization of dynamic CMOS logic and in the field of on-line error detection. It has been shown earlier, that UGNs can be tested completely for delay faults with 'universal' test sets. This result even holds for designs which are not completely path delay testable, since the above test sets check the temporal correctness of a circuit by testing 'path systems' instead of single paths. A universal test set only depends on the computed function and thus, is valid for any unate gate network implementation of this function. This universal test property has to be paid by an increase in test set size, since a design independent test set will in general be larger than a design dependent one. In this paper, we show how to tailor a universal test set to a specific design in order to reduce its size maximally without losing test quality. Experimental results demonstrate that the resulting delay test sets are very compact, and large savings in test set size of up to 96.71% can be achieved compared to the universal test set.