Partially parallel scan chain for test length reduction by using retiming technique

This paper presents a design-for-testability technique aimed at test length reduction for scan designed circuits. A new concept, called partially parallel scan chain, is introduced. In the partially parallel scan chain, some flip-flops are arranged in parallel so that the number of scan shift clocks is reduced. Retiming techniques are used to select the flip-flops arranged in parallel. The flip-flops are repositioned only during test vector generation, but not actually. Then the test vectors generated for the retimed circuit are applied to the original circuit. In this paper, the difference in detectability of faults between the retimed circuit and the original circuit is also discussed. Finally experimental results are shown.