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2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

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Reliability concern induced by TOW and TIM overlay issue in EEPROM EEPROM中TOW和TIM叠加问题引起的可靠性问题
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232647
Weihai Fan, Shunwang Chiang, Stephen Xie, Shaha Hu
{"title":"Reliability concern induced by TOW and TIM overlay issue in EEPROM","authors":"Weihai Fan, Shunwang Chiang, Stephen Xie, Shaha Hu","doi":"10.1109/IPFA.2009.5232647","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232647","url":null,"abstract":"We investigated the overlay effect of TOW (Tunnel Oxide Window) and TIM (Tunneling Implant) on the reliability of EEPROM product. Normally soft failure could be observed on the zero time state devices. The two key reliability indices for non-volatile memory are cycling and data retention. These reliability performances are impacted by the TIM/TOW overlay even with the more strict pre-screening method had been applied due to early failure screening. In this paper a failure model was proposed to explain the failure mechanism. The marginal reliability performance and the faster device degradation during write/ erase cycling or baking could result from the overlay issue of TOW and TIM.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117183946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The irradiation effect and failure analysis of DC-DC power converter DC-DC功率变换器的辐照效应及失效分析
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232625
Yujuan He, Y. En, Hongwei Luo, Xiaoqi He
{"title":"The irradiation effect and failure analysis of DC-DC power converter","authors":"Yujuan He, Y. En, Hongwei Luo, Xiaoqi He","doi":"10.1109/IPFA.2009.5232625","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232625","url":null,"abstract":"The irradiation response of a DC-DC power converter was studied. During the test, the characteristic parameter of DC-DC power converter such as input current and output voltage increased slowly with empty load, and DC-DC power converter was unsteady and the characteristic parameter was strongly influenced by the total-dose when fully loaded. It was indicated that failure of DC-DC converter was due to the source and drain of VDMOSFET fused together because of over power.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116236735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Best test pattern failure analysis flow for functional logic failure localization by IR-OBIRCH technique 基于IR-OBIRCH技术的功能逻辑故障定位的最佳测试模式故障分析流程
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232672
A. Machouat, G. Haller, V. Goubier, D. Lewis, P. Perdu, V. Pouget, F. Essely
{"title":"Best test pattern failure analysis flow for functional logic failure localization by IR-OBIRCH technique","authors":"A. Machouat, G. Haller, V. Goubier, D. Lewis, P. Perdu, V. Pouget, F. Essely","doi":"10.1109/IPFA.2009.5232672","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232672","url":null,"abstract":"The optical IR-OBIRCh technique is a standard failure analysis tool used to localize defects that are located at interconnects layers levels. For a functional logic failure, a failing test pattern is used to condition the device into a particular logic state to generate the failure. Commonly, the defect is detected for a set of test patterns. All test patterns will not provide the same IR-OBIRCh response. A random selection of test patterns may not lead to localize the defect by IR-OBIRCh technique or give fake results. We have performed an extended study of IR-OBIRCh response of a functional logic failure in function of test patterns. Based on these results a best test pattern failure analysis flow has been developed and implemented in order to localize a functional logic failure with IR-OBIRCh technique.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122982546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Acting capability of flux for Pb-free interconnection in electronics assembly 电子装配中无铅互连焊剂的作用性能
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232721
C. Du, Jing Zhao, Yunfei Du, Fang Chen, H. Zhao
{"title":"Acting capability of flux for Pb-free interconnection in electronics assembly","authors":"C. Du, Jing Zhao, Yunfei Du, Fang Chen, H. Zhao","doi":"10.1109/IPFA.2009.5232721","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232721","url":null,"abstract":"The components and characteristics of flux used for Pb-free interconnection are discussed. Applying physical chemistry principles, the decisive factors, activation capability and limit of the flux's activity are analyzed. The results show that special flux must be used in Pb-free interconnections, and acting capability of flux mainly depends on the selected activator, and the built-up activator is an effective way to elevate activity. Flux with high activity can significantly enhance σs-f and reduce σl-f, but it can not reduce σs-l effectively. It is a basic reason why activity is difficult to exert. Reducing the fast growth of inter-metallic compound (IMC) at the interface is a vital measure to improve acting capability of flux.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121081645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Infrared characteristics of ni-doped ZnO thin films ni掺杂ZnO薄膜的红外特性
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232578
Jinghua Jiang, D. He, Yongsheng Wang, M. Fu, B. Feng, Changbin Ju, Yu-fan Du
{"title":"Infrared characteristics of ni-doped ZnO thin films","authors":"Jinghua Jiang, D. He, Yongsheng Wang, M. Fu, B. Feng, Changbin Ju, Yu-fan Du","doi":"10.1109/IPFA.2009.5232578","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232578","url":null,"abstract":"Ni-doped ZnO(ZnO:Ni)thin film had been studied widely as a ferromagnetic semiconductor, but there are far fewer studies on its infrared characteristics. This paper describes experiments in which Ni-doped ZnO thin films were deposited on quartz glass using a sol-gel process with different sintering temperatures. The infrared characteristics and the effects of the different fabrication processes were investigated using various techniques including X-ray diffraction (XRD), SEM and FT-IR.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124117768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure analysis of odd/even word-line failure to improve the endurance performance of a NAND Flash 提高NAND闪存持久性能的奇/偶字行失效分析
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232715
Young Sun, Mark Zhang, Jossen Yu, W. Dong, W. Chien
{"title":"Failure analysis of odd/even word-line failure to improve the endurance performance of a NAND Flash","authors":"Young Sun, Mark Zhang, Jossen Yu, W. Dong, W. Chien","doi":"10.1109/IPFA.2009.5232715","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232715","url":null,"abstract":"A full-flow failure analysis (FA) was introduced in this paper. From the FA, we resolved odd/ even word-line failure which lead to poor endurance performance of a NAND Flash. After removing this defect, the endurance performance of this NAND Flash is greatly enhanced.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"8 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126270667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Anomalous “sweeping stress” induced degradation in n-type low temperature poly-Si thin film transistors n型低温多晶硅薄膜晶体管的异常“横扫应力”诱发退化
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232717
Dapeng Zhou, Mingxiang Wang, Meng Zhang, Han Hao, Dongli Zhang, M. Wong
{"title":"Anomalous “sweeping stress” induced degradation in n-type low temperature poly-Si thin film transistors","authors":"Dapeng Zhou, Mingxiang Wang, Meng Zhang, Han Hao, Dongli Zhang, M. Wong","doi":"10.1109/IPFA.2009.5232717","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232717","url":null,"abstract":"Anomalous “sweeping stress” induced degradation is first observed in n-type metal-induced laterally crystallized low temperature thin film transistors (TFTs). Key stress parameters include the maximum drain bias, the sweeping time and the number of sweeping. Degradation occurs only when the maximum drain bias exceeds a critical value. Both transfer and output characteristic degradation is found much similar to that of hot carrier (HC) degradation. But longer sweeping time causes larger degradation, which is opposite to that in dynamic HC degradation. Besides, such degradation can only be observed in low temperature crystallized TFTs.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129415785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel method for determing the lifetime of devices based on process-stress accelerated degradation test 一种基于过程应力加速退化试验确定器件寿命的新方法
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232608
Guo Chunsheng, Bai Yunxia, Zhang Yuezong, Man Weidong, F. Shiwei, Lv Changzhi, L. Zhiguo
{"title":"A novel method for determing the lifetime of devices based on process-stress accelerated degradation test","authors":"Guo Chunsheng, Bai Yunxia, Zhang Yuezong, Man Weidong, F. Shiwei, Lv Changzhi, L. Zhiguo","doi":"10.1109/IPFA.2009.5232608","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232608","url":null,"abstract":"A novel method, which enables rapid determination of lifetime for semiconductor devices, is presented based on progressive-stress accelerated degradation test. Through two steps of acceleration: firstly, using process-stress accelerated test to accelerate the parameter degradation; secondly, using the data of 1∼5% degradation to extrapolate the data of 10∼50% degradation, this method shortens the test time to dozens or several hundreds of hours. To demonstrate the application of the method, a kind of mature products, Si PNP BJT 3CG120, was tested.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128477687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Failure analysis of VDMOS in DC/DC converter DC/DC变换器中VDMOS失效分析
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232626
Y. Liu, Ch. Y. Huang, N. N. Shan, C. Lu, G. Gao
{"title":"Failure analysis of VDMOS in DC/DC converter","authors":"Y. Liu, Ch. Y. Huang, N. N. Shan, C. Lu, G. Gao","doi":"10.1109/IPFA.2009.5232626","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232626","url":null,"abstract":"In this paper, the failure mechanism of VDMOS in DC/DC converter was analyzed in detail. The result was gained by the reliability project that included reliability experiment and reliability analysis. The VDMOS devices were used in the circuit of DC/DC converter which can achieve the function of 28V into 15V. The accelerated life test was imposed on the VDMOS of the circuit, which has the temperature stress 5°C/day and the electrical stress. The test was began at 75°C, and the VDMOS devices failed at 215 °C. Then the failure analysis which recurred to the failure analysis tools such as the photon emission analysis (PEM) and the physical failure analysis (PFA) to the failed device showed the failure mechanism which is junction-break-down leakage inside source contact, under source wire bond. And the possible root cause of failure probably is Al spiking / diffusion into source contact causing junction leakage under reliability test condition of bias and temp. So in this way, the reliability of VDMOS in DC/DC converter can be tested and evaluated effectively.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128699985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Using STEM with quasi-parallel illumination and an automated peak-finding routine for strain analysis at the nanometre scale 使用STEM与准平行照明和自动峰查找例行应变分析在纳米尺度
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232604
E. Sourty, J. Stanley, Bert Freitag
{"title":"Using STEM with quasi-parallel illumination and an automated peak-finding routine for strain analysis at the nanometre scale","authors":"E. Sourty, J. Stanley, Bert Freitag","doi":"10.1109/IPFA.2009.5232604","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232604","url":null,"abstract":"Strain engineering has become an important tool to allow the semiconductor industry to meet roadmap requirements for device performance in the face of limits to device scaling. In addition, strain and/or lattice distortion through chemistry or mechanical stress, can have significant effect on mechanical, electrical and magnetic properties in a wide range of materials. Therefore, determination of strain in a processed, failed or natural sample will have ramifications in almost all fields of material science and solid state physics. Currently, only transmission electron microscopy (TEM) has proven capable of measuring such buried strains at the required spatial resolutions. This contribution presents an automated methodology to measure strain with high accuracy, high reproducibility, and high spatial resolution yet without the need for elaborate experimental setup or highly trained operator. The methodology is first put in perspective and compared to other available methodologies. Important aspects of the experimental setup are then detailed as well as the specificity of the methodology and used algorithm. Three different cases are described: SiGe multilayer, strained transistor, and indented sapphire and the strain measured discussed.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122433129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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