Weihai Fan, Shunwang Chiang, Stephen Xie, Shaha Hu
{"title":"Reliability concern induced by TOW and TIM overlay issue in EEPROM","authors":"Weihai Fan, Shunwang Chiang, Stephen Xie, Shaha Hu","doi":"10.1109/IPFA.2009.5232647","DOIUrl":null,"url":null,"abstract":"We investigated the overlay effect of TOW (Tunnel Oxide Window) and TIM (Tunneling Implant) on the reliability of EEPROM product. Normally soft failure could be observed on the zero time state devices. The two key reliability indices for non-volatile memory are cycling and data retention. These reliability performances are impacted by the TIM/TOW overlay even with the more strict pre-screening method had been applied due to early failure screening. In this paper a failure model was proposed to explain the failure mechanism. The marginal reliability performance and the faster device degradation during write/ erase cycling or baking could result from the overlay issue of TOW and TIM.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"116 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2009.5232647","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We investigated the overlay effect of TOW (Tunnel Oxide Window) and TIM (Tunneling Implant) on the reliability of EEPROM product. Normally soft failure could be observed on the zero time state devices. The two key reliability indices for non-volatile memory are cycling and data retention. These reliability performances are impacted by the TIM/TOW overlay even with the more strict pre-screening method had been applied due to early failure screening. In this paper a failure model was proposed to explain the failure mechanism. The marginal reliability performance and the faster device degradation during write/ erase cycling or baking could result from the overlay issue of TOW and TIM.