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Passive DNA Sensor with Gold Electrodes Fabricated in a CMOS Backend Process 基于CMOS后端工艺的金电极被动DNA传感器
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194974
F. Hofmann, A. Frey, B. Holzapfl, M. Schienle, C. Paulus, P. Schindler-Bauer, R. Thewes, R. Hintsche, E. Nebling, J. Albers, W. Gumbrecht
{"title":"Passive DNA Sensor with Gold Electrodes Fabricated in a CMOS Backend Process","authors":"F. Hofmann, A. Frey, B. Holzapfl, M. Schienle, C. Paulus, P. Schindler-Bauer, R. Thewes, R. Hintsche, E. Nebling, J. Albers, W. Gumbrecht","doi":"10.1109/ESSDERC.2002.194974","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194974","url":null,"abstract":"A sensor for electrical detection of DNA is fabricated in a CMOS production line. A gold deposition process module is integrated in a CMOS backend process. The sensor principle is based on immobilization of singlestranded DNA probe molecules on an array consisting of interdigitated gold lines and subsequent hybridization with labeled target DNA strands. The electrical signal results from an electrochemical redox cycling process. Successful DNA detection experiments on the basis of such ‘passive’ chips are performed. This passive arrangement represents a test run for the extension of this principle to develop fully electronic DNA sensor arrays on active CMOS chips.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123874991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Silicon Single-electron Devices for Logic Applications 逻辑应用硅单电子器件
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194872
Y. Takahashi
{"title":"Silicon Single-electron Devices for Logic Applications","authors":"Y. Takahashi","doi":"10.1109/ESSDERC.2002.194872","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194872","url":null,"abstract":"The single-electron device (SED) is drawing a lot of attention for future large-scale integration because of its low-power nature and small size. We have developed a novel method called pattern-dependent oxidation (PADOX) for fabricating small Si single-electron transistors (SETs) and used it to make many kinds of SEDs. One of the most primitive and important SEDs that we have demonstrated is a quasi-CMOS type inverter that has voltage gain larger than unity. The inverter utilizes a SET as a switch, although it acts as both p-type and ntype switches. In addition, SETs have two unique features that conventional transistors do not have. One is multiinput gates capability, and the other is oscillatory conductance as a function of gate voltage. We have exploited these features to achieve complicated functions, such as an adder and a multiple-valued memory. In addition, we have developed a single-electron CCD that enables us to manipulate a single electron without tunnel capacitors. The device utilizes small Si-wire MOSFETs connected in series, and an elementary charge can be transferred like in a CCD.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124912397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits 缩放SOI CMOS在高频模拟电路中的适用性
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194980
N. Zamdmer, J. Plouchart, Jonghae Kim, Liang-Hung Lu, S. Narasimha, P. O'Neil, A. Ray, M. Sherony, L. Wagner
{"title":"Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits","authors":"N. Zamdmer, J. Plouchart, Jonghae Kim, Liang-Hung Lu, S. Narasimha, P. O'Neil, A. Ray, M. Sherony, L. Wagner","doi":"10.1109/ESSDERC.2002.194980","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194980","url":null,"abstract":"In this paper we show that the ability of SOI NMOS transistors to function as high-bandwidth amplifiers continuously improves as gate length shrinks below 50 nm. fT of 196 GHz is achieved at Lpoly = 47 nm. Neither the transconductance nor the input capacitance reaches a limiting value at Lpoly = 47 nm. The gate sheet resistance, which influences the FET input resistance and high-frequency noise, shows little variation and is an acceptable value (7: /square) in the Lpoly = 55 nm to 77 nm range. We also present four features of an aggressively scaled 0.13-Pm partially-depleted SOI CMOS technology that show its suitability for high-frequency circuit applications: RF noise performance comparable to state-of-the art III-V devices, body-tied SOI FETs that achieve the same low-frequency noise as bulk FETs, a multilevel back-end that allows high-density and high-Q passives, and negligible floating-body-induced jitter in RF circuits. 1. FET scaling","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125840311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Application of Polycrystalline SiGe for Gain Control in SiGe Heterojunction Bipolar Transistors 多晶SiGe在SiGe异质结双极晶体管增益控制中的应用
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194897
V. D. Kunz, C. D. de Groot, S. Hall, I. Anteney, A.I. Abdul-Rahim, P. Ashburn
{"title":"Application of Polycrystalline SiGe for Gain Control in SiGe Heterojunction Bipolar Transistors","authors":"V. D. Kunz, C. D. de Groot, S. Hall, I. Anteney, A.I. Abdul-Rahim, P. Ashburn","doi":"10.1109/ESSDERC.2002.194897","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194897","url":null,"abstract":"This paper reports a method of controlling the gain of a bipolar transistor by incorporating Ge in the polysilicon emitter. Measured results show that varying the Ge content in the polySiGe from 0 to 33% gives a change in base current of approximately four. The competing influences of the Ge and the interfacial layer at the polySiGe/Si interface are investigated theoretically using an effective surface recombination velocity for the polySiGe emitter. Good agreement between theory and measured results is obtained. When incorporated into a SiGe HBT, the polySiGe emitter will allow the best trade-off between gain and BVCEO to be achieved for a given Ge and B profile in the base.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114531934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient Monte Carlo Simulation of Tunnel Currents in MOS Structures MOS结构隧道电流的高效蒙特卡罗模拟
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194899
D. Grgec, M. Vexler, C. Jungemann, B. Meinerzhagen
{"title":"Efficient Monte Carlo Simulation of Tunnel Currents in MOS Structures","authors":"D. Grgec, M. Vexler, C. Jungemann, B. Meinerzhagen","doi":"10.1109/ESSDERC.2002.194899","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194899","url":null,"abstract":"In this paper, a new efficient model for the evaluation of tunnel currents in MOS struactures for Monte Carlo device simulation is presented. Several methods for tunneling probability calculation can be used and the model has the important advantage of being compatible with the modified local density approximation for quantum correction of the carrier density. Implementation of the model in a Monte Carlo device simulaton is explained. Simulations of test MOSFETs and comparisons with measurements are presented.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130153589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Controlling STI-related Parasitic Conduction in 90 nm CMOS and Below 在90纳米及以下CMOS中控制sti相关寄生导通
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194979
E. Augendre, R. Rooyackers, D. Shamiryan, C. Ravit, M. Jurczak, G. Badenes
{"title":"Controlling STI-related Parasitic Conduction in 90 nm CMOS and Below","authors":"E. Augendre, R. Rooyackers, D. Shamiryan, C. Ravit, M. Jurczak, G. Badenes","doi":"10.1109/ESSDERC.2002.194979","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194979","url":null,"abstract":"In parallel to its continuous scaling, shallow trench isolation (STI) requires thorough optimisation with respect to its impact on device performance. In particular, the conduction occurring at the isolation edge of the device needs to be limited. Among the factors that influence the related control of threshold voltage and subthreshold current, this paper evaluates the impact of process parameters such as transistor architecture, trench profile (conventional or T-shape) and, for the first time, sacrificial oxidation strategy. It is first proven that conventional STI architecture can provide the same gate oxide integrity and control of lateral conduction as T-shape STI. Second, it is shown that transistor scaling improves immunity to narrow channel effects. This is illustrated with an optimised conventional STI module showing hump-free operation and threshold voltage variation of 40 mV down to 0.11 µm wide nMOS transistors, making the approach suitable at least down to the 90 nm technology node.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130226621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Metal Rings as Quantum Bits 作为量子比特的金属环
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.195006
C. Kerner, W. Magnus, W. Schoenmaker
{"title":"Metal Rings as Quantum Bits","authors":"C. Kerner, W. Magnus, W. Schoenmaker","doi":"10.1109/ESSDERC.2002.195006","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.195006","url":null,"abstract":"We propose a device that meets the physical and quantum mechanical conditions required for the operation of interacting quantumbits. Metal rings embeddedin a solid state substrate by means of silicon processing technology are considered as the basic computing elements. We investigate different set-ups and concepts that are compatible with the topology of the metallic rings. Accessing the rings for in- and output signals as well as achieving the exchange and quantization of information are two essential requirements for a proper operation of an array of communicating quantum bits. In particular, the superposition of the quantum states characterizing the quantum bit array is primordial in order to run quantumcomputing algorithms. Furthermore, decoherence must be dealt with in a controllable fashion in order to read out the signals before they loose the signature of the quantum information. This work reports on the processing and testing of two device configurations.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130344341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Tunnel Oxide Thickness on Erratic Erase in Flash Memories 隧道氧化物厚度对闪存中非稳定擦除的影响
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194944
A. Chimenton, P. Olivo
{"title":"Impact of Tunnel Oxide Thickness on Erratic Erase in Flash Memories","authors":"A. Chimenton, P. Olivo","doi":"10.1109/ESSDERC.2002.194944","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194944","url":null,"abstract":"Fowler-Nordheim erase in Flash Memories is intrinsically affected by the erratic phenomenon whose origin has physical aspects that are still obscure. This work presents new experimental results showing the impact of the oxide thickness on the erratic erase during cycling. The collected statistical results play a key role for the study of the charging/discharging properties of tunneling oxides.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122991768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Substrate Effects on the Small-Signal Characteristics of SOI MOSFETs 衬底对SOI mosfet小信号特性的影响
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194982
V. Kilchytska, D. Levacq, D. Lederer, J. Raskin, D. Flandre
{"title":"Substrate Effects on the Small-Signal Characteristics of SOI MOSFETs","authors":"V. Kilchytska, D. Levacq, D. Lederer, J. Raskin, D. Flandre","doi":"10.1109/ESSDERC.2002.194982","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194982","url":null,"abstract":"The present paper investigates the influence of the silicon substrate on the AC characteristics of fully-depleted (FD) and partially-depleted (PD) silicon-on-insulator (SOI) MOSFETs. For the first time it is shown that the presence of the substrate underneath the buried oxide results in two transitions (i.e. zero-pole doublets) in the output conductance vs frequency characteristics, depending on the space-charge conditions at the buried oxide-substrate interface. The paper discusses the analytical device modelling to include the influence of the substrate in CAD circuit simulations.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117013252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High-performance Silicon-On-Glass VDMOS Transistor for RF-Power Applications 用于射频功率应用的高性能玻璃上硅VDMOS晶体管
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194948
N. Nenadovic, W. Cuoco, M.P. van de Heijden, L. Nanver, J. Slotboom, S. Theeuwen, H. Jos
{"title":"High-performance Silicon-On-Glass VDMOS Transistor for RF-Power Applications","authors":"N. Nenadovic, W. Cuoco, M.P. van de Heijden, L. Nanver, J. Slotboom, S. Theeuwen, H. Jos","doi":"10.1109/ESSDERC.2002.194948","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194948","url":null,"abstract":"A complete analysis of DC and RF performance of a novel SOI vertical DMOS transistor on glass and a conventional LDMOS transistor for RF power applications is presented. The analysis is based on MEDICI device simulations and the ”Smoothie” database model for FET devices. An SOI VDMOST on glass with a breakdown of 115V, a specific on-resistance RONSP of 3mΩcm 2 ,a n fTmax of 7.4 GHz at VDS=26V and a saturation current of 1.25·10 �4 A/µ ma t VDS=10V is demonstrated. A device with 1mm long gate has PAE of 43% and power gain of 18.5 dB with 1dB compression point at POUT=26dBm. Since this SOI VDMOS device shows better linearity and higher power gain compared to conventional LDMOST, it would be the device of choice for RF power applications. Moreover, silicon-on-glass technology offers integration with high quality passives and the possibility to electroplate copper heat sinks only a few microns away from the active device area. Both features are very important for development of integrated power amplifiers.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124180697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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