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On Increasing the Accuracy of Simulations of Deposition and Etching Processes Using Radiosity and the Level Set Method 利用辐射和水平集方法提高沉积和蚀刻过程模拟的精度
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194940
C. Heitzinger, J. Fugger, Oliver Häberlen, Siegfried Selberherr
{"title":"On Increasing the Accuracy of Simulations of Deposition and Etching Processes Using Radiosity and the Level Set Method","authors":"C. Heitzinger, J. Fugger, Oliver Häberlen, Siegfried Selberherr","doi":"10.1109/ESSDERC.2002.194940","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194940","url":null,"abstract":"Deposition and etching in Silicon trenches is an important step of today’s semiconductor manufacturing. Understanding the surface evolution enables to predict the resulting profiles and thus to optimize process parameters. Simulations using the radiosity modeling approach and the level set method provide accurate results, but their speed has to be considered when employing advanced models and for purposes of inverse modeling. In this paper strategies for increasing the accuracy of deposition simulations while decreasing simulation times are presented. Two algorithms were devised: first, intertwining narrow banding and extending the speed function yields a fast and accurate level set algorithm. Second, an algorithm which coarsens the surface reduces the computational demands of the radiosity method. Finally measurements of a typical TEOS deposition process are compared with simulation results both with and without coarsening of the surface elements. It was found that the computational effort is significantly reduced without sacrificing the accuracy of the simulations.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115751629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Inversion Layer Quantization Impact on the Interpretation of 1/f Noise in Deep Submicron CMOS Transistors 反演层量化对深亚微米CMOS晶体管1/f噪声解释的影响
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194875
A. Mercha, E. Simoen, G. Richardson, C. Claeys
{"title":"Inversion Layer Quantization Impact on the Interpretation of 1/f Noise in Deep Submicron CMOS Transistors","authors":"A. Mercha, E. Simoen, G. Richardson, C. Claeys","doi":"10.1109/ESSDERC.2002.194875","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194875","url":null,"abstract":"This paper discusses the impact of inversion layer quantization on the interpretation of the 1/f noise characteristics in deep submicron CMOS transistors. In order to describe the strong gate voltage dependence of the input-referred noise spectral density, a model will be developed which consistently takes account of inversion layer quantization. The only adjustable parameter is the density of near interface oxide traps, which sets the level of the flat-band voltage noise spectral density in weak inversion. It is shown that a good agreement with measured data obtained on 0.13 µm CMOS transistors is found both for n– and p-channel devices. Finally, the implications with respect to practical noise modeling will be discussed.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127085537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact of ALCVD and PVD Titanium Nitride Deposition on Metal Gate Capacitors ALCVD和PVD氮化钛沉积对金属栅极电容器的影响
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194998
G. Lujan, T. Schram, L. Pantisano, J. Hooker, S. Kubicek, E. Rohr, J. Schuhmacher, O. Kilpela, H. Sprey, S. De Gendt, K. De Meyer
{"title":"Impact of ALCVD and PVD Titanium Nitride Deposition on Metal Gate Capacitors","authors":"G. Lujan, T. Schram, L. Pantisano, J. Hooker, S. Kubicek, E. Rohr, J. Schuhmacher, O. Kilpela, H. Sprey, S. De Gendt, K. De Meyer","doi":"10.1109/ESSDERC.2002.194998","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194998","url":null,"abstract":"In this paper it will be shown that the deposition method is an important parameter for the electrical properties of the metal gate. Indeed, ALCVD(Atomic Layer Chemical Vapor Deposition) TiN metal has a 5.3eV workfunction, suitable for PMOS devices. The PVD sputtered (Physical Vapor Deposition) TiN has a lower workfunction around 4.8eV and is mid-gap like. The PVD TiN capacitors have a higher effective oxide charge than the ALCVD capacitors as extracted from capacitance measurements and from workfunction calculations. PVD TiN also exhibits process-induced damage as seen from leakage measurements.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127487408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Extraction of Si-SiO2 Interface Trap Densities in MOSFET's with Oxides Down to 1.3 nm Thick 在厚度为1.3 nm的MOSFET中提取Si-SiO2界面阱密度
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194912
D. Bauza
{"title":"Extraction of Si-SiO2 Interface Trap Densities in MOSFET's with Oxides Down to 1.3 nm Thick","authors":"D. Bauza","doi":"10.1109/ESSDERC.2002.194912","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194912","url":null,"abstract":"It is shown that reliable interface trap density values can be extracted from MOS devices with ultrathin oxides by using charge pumping and small gate voltage swings. This presents three advantages with respect to the conventional large gate voltage swing approach: the extraction is simple as carrier emission do not contribute to the CP signal so that the CP current magnitude directly reflects the interface trap density; the tunneling current is strongly reduced allowing a more easy extraction of the CP signal; this prevents the insulator and the insulator-silicon interface from any degradation. By doing so, interface trap densities from MOS devices with oxides down to 1.3 nm thick are reported for the first time.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123694446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Tunnelling and Impact Ionization in Scaled Double Doped PHEMTs 双掺杂PHEMTs的隧道效应与冲击电离
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194929
K. Kalna, A. Asenov
{"title":"Tunnelling and Impact Ionization in Scaled Double Doped PHEMTs","authors":"K. Kalna, A. Asenov","doi":"10.1109/ESSDERC.2002.194929","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194929","url":null,"abstract":"We investigate the dominant breakdown mechanism in aggressively scaled pseudomorphic high electron mobility transistors (PHEMTs) with double delta-doping structure by Monte Carlo device simulations. Two breakdown mechanisms: channel impact ionization and thermionic tunnelling from the gate, are considered for two possible placements of the second delta doping layer either below the channel or between the gate and the first delta doping layer. Thermionic tunnelling starts at very low drain voltages but quickly saturates having a greater effect on those PHEMTs with the second doping layer placed above the original doping. A threshold for impact ionization occurs at larger drain voltages which should assure the reasonable operation voltage scale of double doped PHEMTs. Those double doped PHEMTs with the second delta doping layer placed below the channeldeteriorate faster with the reduction of the channel length due to impact ionization thanthosedeviceswith theseconddopinglayerabove the original doping.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115330653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integrated Si-based Opto-Couplers: a Novel Approach to Galvanic Isolation 集成硅基光耦合器:一种电流隔离的新方法
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.195014
A. Alessandria, L. La Magna, M. Renna, L. Fragapane, S. Coffa
{"title":"Integrated Si-based Opto-Couplers: a Novel Approach to Galvanic Isolation","authors":"A. Alessandria, L. La Magna, M. Renna, L. Fragapane, S. Coffa","doi":"10.1109/ESSDERC.2002.195014","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.195014","url":null,"abstract":"In many applications the need of galvanic isolation for safety or functional requirements is very high. In this paper a new isolated opto-coupler device concept is presented. Our approach combines an isolation technology with the integration of a silicon-based optical transmission system. This new concept enhances design, flexibility, performances and reliability of the devices, resulting in space and cost saving. In the first section two isolation technologies will be presented. Subsequently, the transmission system will be elucidated. At last a case of application in the field of power devices will be presented.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116571687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Impact of Deep N-well Implantation on Substrate Noise Coupling and RF Transistor Performance for Systems-on-a-Chip Integration 深n阱植入对片上系统集成中衬底噪声耦合和射频晶体管性能的影响
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194917
K. Chew, J. Zhang, K. Shao, W. Loh, S. Chu
{"title":"Impact of Deep N-well Implantation on Substrate Noise Coupling and RF Transistor Performance for Systems-on-a-Chip Integration","authors":"K. Chew, J. Zhang, K. Shao, W. Loh, S. Chu","doi":"10.1109/ESSDERC.2002.194917","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194917","url":null,"abstract":"This paper reviews the merits of incorporating deep n-well implantation in state-of-the-art CMOS technologies to address mixed-mode coupling in integrated circuits. The deep n-well architecture, coupled with novel body biasing techniques and the use of p+ guard ring, have resulted in a maximum of 35 dB reduction in substrate noise at 100 MHz. Furthermore the deep n-well implantation does not impact the dc, ac, rf and noise performance of the multi-fingered transistor, hence allowing model consistency with the standard well multi-fingered transistor.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114428727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Experimental Verification of the Smoothie Database Model for Third and Fifth Order Intermodulation Distortion 三阶和五阶互调失真的Smoothie数据库模型实验验证
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.195011
V. Cuoco, M.P. van de Heijden, M. Pelk, L. D. de Vreede
{"title":"Experimental Verification of the Smoothie Database Model for Third and Fifth Order Intermodulation Distortion","authors":"V. Cuoco, M.P. van de Heijden, M. Pelk, L. D. de Vreede","doi":"10.1109/ESSDERC.2002.195011","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.195011","url":null,"abstract":"The experimental intermodulation verification of the Smoothie table-based model for FET devices is presented. The model is implemented in the Agilent’s Advanced Design System (ADS) circuit simulation program and is based on the smoothing spline approximation of the device Y-parameters. The device main functions, i.e. the terminal currents and charges, are calculated by the analytical line integration of the Y-parameters. The use of smoothing splines yields continuous higher order derivatives and, consequently, the correct simulation of higher order intermodulation products. The latter is of paramount importance in the development of 3G PA applications. The results presented show excellent agreement between the measured and modelled intermodulation distortion as function of bias and power.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129744732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Simulation of High-K Tunnel Barriers for Nonvolatile Floating Gate Memories 非易失性浮栅存储器的高k隧道势垒模拟
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.195002
M. Specht, M. Stadele, F. Hofmann
{"title":"Simulation of High-K Tunnel Barriers for Nonvolatile Floating Gate Memories","authors":"M. Specht, M. Stadele, F. Hofmann","doi":"10.1109/ESSDERC.2002.195002","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.195002","url":null,"abstract":"Replacing silicon dioxide tunnel dielectrics in nonvolatile floating gate memories by high-K materials may pave the way to continued scaling of state of the art flash memories. To evaluate the requirements for barrier height, programming voltages and injection speed, we have calculated WKB currents through single layer and multilayer high-K based dielectrics. For a single layer minimal barrier height of about 2eV, limited by thermionic current, we find Fowler-Nordheim programming voltages of about 7-9V. In order to further reduce the voltage or enhance the injection tunnel current, symmetric triple layers of sequence low-K/highK/low-K are proposed. Asymmetric structures are also briefly discussed.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124117529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Monolithic Integration of a Novel Microfluidic Device with Silicon Light Emitting Diode-Antifuse and Photodetector 一种新型微流控器件与硅发光二极管-反熔断和光电探测器的单片集成
32nd European Solid-State Device Research Conference Pub Date : 2002-09-24 DOI: 10.1109/ESSDERC.2002.194965
P. LeMinh, J. Holleman, J. Berenschot, N. Tas, A. van den Berg
{"title":"Monolithic Integration of a Novel Microfluidic Device with Silicon Light Emitting Diode-Antifuse and Photodetector","authors":"P. LeMinh, J. Holleman, J. Berenschot, N. Tas, A. van den Berg","doi":"10.1109/ESSDERC.2002.194965","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194965","url":null,"abstract":"Light emitting diode antifuse has been integrated into a microfluidic device that is realized with extended standard CMOS technological steps. The device comprises of a microchannel sandwiched between a photodiode detector and a nanometer-scale diode antifuse light emitter. In this chapter, the device fabrication process, working principle and properties will be discussed. Change in the interference fringe of the antifuse spectra has been measured due to the filling of the channel. Preliminary possible applications are electro-osmotic flow speed measurement, detection of absorptivity of liquids in the channel…","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125665755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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