Impact of Deep N-well Implantation on Substrate Noise Coupling and RF Transistor Performance for Systems-on-a-Chip Integration

This paper reviews the merits of incorporating deep n-well implantation in state-of-the-art CMOS technologies to address mixed-mode coupling in integrated circuits. The deep n-well architecture, coupled with novel body biasing techniques and the use of p+ guard ring, have resulted in a maximum of 35 dB reduction in substrate noise at 100 MHz. Furthermore the deep n-well implantation does not impact the dc, ac, rf and noise performance of the multi-fingered transistor, hence allowing model consistency with the standard well multi-fingered transistor.