{"title":"非易失性浮栅存储器的高k隧道势垒模拟","authors":"M. Specht, M. Stadele, F. Hofmann","doi":"10.1109/ESSDERC.2002.195002","DOIUrl":null,"url":null,"abstract":"Replacing silicon dioxide tunnel dielectrics in nonvolatile floating gate memories by high-K materials may pave the way to continued scaling of state of the art flash memories. To evaluate the requirements for barrier height, programming voltages and injection speed, we have calculated WKB currents through single layer and multilayer high-K based dielectrics. For a single layer minimal barrier height of about 2eV, limited by thermionic current, we find Fowler-Nordheim programming voltages of about 7-9V. In order to further reduce the voltage or enhance the injection tunnel current, symmetric triple layers of sequence low-K/highK/low-K are proposed. Asymmetric structures are also briefly discussed.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Simulation of High-K Tunnel Barriers for Nonvolatile Floating Gate Memories\",\"authors\":\"M. Specht, M. Stadele, F. Hofmann\",\"doi\":\"10.1109/ESSDERC.2002.195002\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Replacing silicon dioxide tunnel dielectrics in nonvolatile floating gate memories by high-K materials may pave the way to continued scaling of state of the art flash memories. To evaluate the requirements for barrier height, programming voltages and injection speed, we have calculated WKB currents through single layer and multilayer high-K based dielectrics. For a single layer minimal barrier height of about 2eV, limited by thermionic current, we find Fowler-Nordheim programming voltages of about 7-9V. In order to further reduce the voltage or enhance the injection tunnel current, symmetric triple layers of sequence low-K/highK/low-K are proposed. Asymmetric structures are also briefly discussed.\",\"PeriodicalId\":207896,\"journal\":{\"name\":\"32nd European Solid-State Device Research Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-09-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"32nd European Solid-State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2002.195002\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"32nd European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2002.195002","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Simulation of High-K Tunnel Barriers for Nonvolatile Floating Gate Memories
Replacing silicon dioxide tunnel dielectrics in nonvolatile floating gate memories by high-K materials may pave the way to continued scaling of state of the art flash memories. To evaluate the requirements for barrier height, programming voltages and injection speed, we have calculated WKB currents through single layer and multilayer high-K based dielectrics. For a single layer minimal barrier height of about 2eV, limited by thermionic current, we find Fowler-Nordheim programming voltages of about 7-9V. In order to further reduce the voltage or enhance the injection tunnel current, symmetric triple layers of sequence low-K/highK/low-K are proposed. Asymmetric structures are also briefly discussed.
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