32nd European Solid-State Device Research Conference最新文献

{"title":"Influence of Source-drain Tunneling on the Subthreshold Behavior of sub-10nm Double-gate MOSFETs","authors":"M. Staedele","doi":"10.1109/ESSDERC.2002.194888","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194888","url":null,"abstract":"A microscopic tight-binding formalism is used to analyze source-drain tunneling and subthreshold currents in very short (< 12 nm) double-gate transistors. Tunneling is found to enhance source-drain currents substantially, especially at low temperatures. We quantify and discuss the corresponding degradation of subthreshold swings and compare with results obtained with the WKB approximation. The energy dependence of the effective tunnel mass is predicted and identified as an additional factor that deteriorates the subthreshold behavior.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116076510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SiGe pMOSFETs Fabricated on Novel SiGe Virtual Substrates Grown on 10um x 10um Pillars","authors":"U. Straube, A. Waite, N. Lloyd, S. Croucher, Y. T. Tang, A. Evans, T. Grasby, T. Whall, E. Parker, T. Norris, T. Cullis","doi":"10.1109/ESSDERC.2002.194885","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194885","url":null,"abstract":"Silicon germanium pMOSFETs have been fabricated on novel silicon germanium virtual substrates. The SiGe virtual substrates were grown by MBE on 10μmx10μm silicon pillars fabricated by dry etching trenches into the original silicon substrate. The pillars promote relaxation of the SiGe virtual substrate and reduce cross hatch on the wafer surface. The devices have 5nm silicon germanium active layer with a germanium content of 70% grown on top of a relaxed virtual substrate with a germanium content of 30%. A 2nm silicon cap separates the SiGe channel from the gate oxide. Device characteristics show a improvement in on state drive current in these SiGe devices of 40% over their conventional silicon counterparts.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"587 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123417937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantum Dot Materials and Devices for Light Emission in Silicon","authors":"M. E. Castagna, S. Coffa, L. Caristia, A. Messina, C. Bongiorno","doi":"10.1109/ESSDERC.2002.194962","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194962","url":null,"abstract":"We report on the fabrication and performances of the most efficient Si-based light sources. The devices consist of MOS structures with erbium (Er) implanted in the thin gate oxide. The devices exhibit strong 1.54 µm electroluminescence at 300K with a 10% external quantum efficiency, comparable to that of standard light emitting diodes using III-V semiconductors. Er excitation is caused by hot electrons impact and oxide wearout limits the reliability of the devices. Much more stable light emitting MOS devices have been fabricated using Er-doped SRO (Silicon Rich Oxide) films as gate dielectric. These devices show a high stability, with an external quantum efficiency reduced to 1%. In these devices Er pumping occurs by energy transfer from the Si nanostructures to the rare earth ions.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121260704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"65 nm Transistors for a 90 nm CMOS SOC Platform","authors":"M. Mirabedini, V. Gopinath, A. Kamath, M.Y. Lee, W. Yeh","doi":"10.1109/ESSDERC.2002.194887","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194887","url":null,"abstract":"Transistors with 65nm physical gate length for a 90 nm node CMOS technology are reported. Current drive of 775/270 A/ m (Ioff=30nA/ m) at 1V was achieved for N/P-Ch transistors using a 16 Å oxynitrided gate dielectric to reduce the gate leakage current. The Nchannel performance is one of the highest reported thus far. Also, impact of process improvements including pre-gate surface clean, choice of contact ILD material and salicide on the transistor performance was demonstrated. These improvements were used to achieve a higher current drive at a fixed off-state leakage current.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126048739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling the C-V Characteristics of Heterodimensional Schottky Contacts","authors":"R. Ragi, J. Manzoli, M. Romero, B. Nabet","doi":"10.1109/ESSDERC.2002.195008","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.195008","url":null,"abstract":"Abstract This paper addresses the capacitance-voltage (C-V)characteristics of heterodimensional Schottky diodes, inwhich the Schottky metal is placed in direct contact toa two-dimensional electron gas and the confinedelectron behavior directly dictates the deviceperformance. We develop a novel quasi-2D model forthe C-V characteristics of the device, by starting from aself-consistent solution of the Schrodinger and Poissonequations in the growth direction. The model isvalidated by contrasting the theoretical results withexperimental data from an AlGaAs/GaAs devicefabricated in our laboratory. 1. Introduction The properties of electrons in an inversion layerhave attracted interest since the 1930’s, when Lilienfeldconceived the field-effect transistor. Further attentionhas been motivated by the enhanced transport propertiesof the two-dimensional electron gas (2-DEG) formed atmodulation doped heterointerfaces, where the inversionlayer isquantized in the growth direction. Already inthe early 90’s High Electron-Mobility Transistors(HEMTs) based on this principle displayed poweramplification well above 100 GHz with outstandingnoise performance.This paper is concerned with devices based on afurther extension of the modulation doping concept byusing heterodimensional interfaces, i.e., interfacesbetween materials of dissimilar dimensions. In ourspecific case, this interface is a Schottky barrier laterallyconnecting a three-dimensional (3D) metal and a two-dimensional (2D) electron gas.In fact, heterodimensional diodes, transistors andphotodetectors present several attractive features such aslow capacitance due to the small effective cross-section,excellent noise and transport characteristics due to the2D electron gas and a high breakdown voltage, makingthem very promising for high-frequency applications [1-2].In order to illustrate the motivation for studyingheterodimensional devices we briefly revisit the questionof computing the thermionic emission current in suchdevices. In fact,straighforward extension of Bethe’stheory, considering both the proper two-dimensionaldensity of states as well as energyquantization in thegrowth direction for a 2-DEG with only onesignificantly populated subband, yields [3]:1 (1)kTqVexpkTEexpkTqJ A* T3 2 exp B","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126176053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Suppression of CoSix Induced Leakage Current Using Novel Capping Process for Sub-0.10um node SRAM Cell Technology","authors":"H. Kwon, B. Hwang, W. Cho, C. Chang, S. Kim, Y. Park, H. Ihm, J.K. Park, H. Kang, J. Jeong, J.B. Park, Y. Jang, S. Jung, K. Kim","doi":"10.1109/ESSDERC.2002.194903","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194903","url":null,"abstract":"We present a novel capping process for sub-0.10um node SRAM cell to suppress the Co silicide induced leakage current. The dimensions in the SRAM cell are scaled down to sub-0.10um. As a result, the CoSix induced leakage current increases as the sizes of the contact and the active area decrease due to the CoSix defects and the contact etch induced CoSix pitting. The double stacked layers on Co silicide successfully reduced the junction leakage current and widened the borderless contact etching process window by suppression of the CoSix defects and the Co silicide pittings.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125197872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance and Reliability of High Density Flash EEPROMs under CHISEL Programming Operation","authors":"S. Mahapatra, S. Shukuri, J. Bude","doi":"10.1109/ESSDERC.2002.194941","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194941","url":null,"abstract":"We demonstrate CHISEL programming operation of fully scaled high-density flash EEPROMs. Single cell program and erase characteristics show reliable operation in terms of programming disturbs and cycling induced degradation. Program and erase operation of high-density arrays show a unique post-erase operation, tight threshold voltage distribution and over 10 years of data retention even after 10 5 program/erase cycles. Results are presented showing the feasibility of CHISEL programming operation for deeply scaled high-density flash EEPROMs.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129734284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechanisms of Dopant Redistribution and Retention in Silicon Following Ultra-low Energy Boron Implantation and Excimer Laser Annealing","authors":"L. Mariucci, G. Fortunato, S. Whelan, V. Privitera, G. Mannino","doi":"10.1109/ESSDERC.2002.195001","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.195001","url":null,"abstract":"Excimer laser annealing (ELA) of ultra-low energy (ULE) B ion implanted Si has been studied and the process has been shown to allow for the formation of ultra-shallow junctions (35 nm) with abrupt profiles (2.5 nm/decade), applicable to the future requirements of semiconductor devices. High resolution transmission electron microscopy has been used to assess the asimplanted damage and the crystal recovery following ELA. The electrical activation of B in Si during ELA has been investigated as a function of laser energy density (melt depth), implantation energy and number of laser pulses (melt time). The activated and retained dose has been evaluated with spreading resistance profiling and secondary ion mass spectrometry. A significant amount of the implanted dopant was not activated following ELA. The fraction of the implanted dopant which was not activated during ELA was lost from the sample through out diffusion. However, the dopant that was retained in crystal material during ELA was fully activated and no defect regions have been observed at the surface and at the liquid-crystal interface position. The electrical activation was increased for high laser energy density annealing when the dopant was redistributed over a deeper range.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130239039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Four-Gate Transistor","authors":"S. Cristoloveanu, B. Blalock, F. Allibert, B. Dufrene, M. Mojarradi","doi":"10.1109/ESSDERC.2002.194934","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194934","url":null,"abstract":"The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130612067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accurate Delay Metric for On-chip Resistive Interconnect","authors":"M. Oulmane, N. Rumin","doi":"10.1109/ESSDERC.2002.194890","DOIUrl":"https://doi.org/10.1109/ESSDERC.2002.194890","url":null,"abstract":"This paper presents a delay metric for resistive interconnect which computes the delay to any point on the waveform at any point along the interconnect. It is based on the first two moments of the impulse response. The empirical D2M metric [I] is shown to be a special case of the one presented here. The metric has proven to be accurate to within 5% of HSPICE simulations.","PeriodicalId":207896,"journal":{"name":"32nd European Solid-State Device Research Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123276263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}