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2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)最新文献

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Transformation conditions of performance fronts of operational amplifiers 运算放大器性能前端的变换条件
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301698
E. Roca, R. Castro-López, M. Velasco, F. Fernández
{"title":"Transformation conditions of performance fronts of operational amplifiers","authors":"E. Roca, R. Castro-López, M. Velasco, F. Fernández","doi":"10.1109/SMACD.2015.7301698","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301698","url":null,"abstract":"Pareto fronts of circuits whose performance depend on other circuits that they are connected to must be updated for each interconnection conditions. This paper reports, for the first time, the conditions for which a transformation without loss of information is guaranteed.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129431298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Surrogate modeling and optimization of inductor performances using Kriging functions 利用Kriging函数对电感器性能进行代理建模和优化
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301675
F. Passos, R. Gonzalez-Echevarria, E. Roca, R. Castro-López, F. Fernández
{"title":"Surrogate modeling and optimization of inductor performances using Kriging functions","authors":"F. Passos, R. Gonzalez-Echevarria, E. Roca, R. Castro-López, F. Fernández","doi":"10.1109/SMACD.2015.7301675","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301675","url":null,"abstract":"Integrated inductors are one of the most important passive elements in RF circuits. However, time-consuming simulations, such as electromagnetic simulations, have to be used to evaluate their performances with high accuracy. In order to overcome this problem, analytical models can be used. In this paper, a surrogate model based on Kriging functions is presented that accurately predicts the performance parameters of integrated inductors. The different approaches followed to obtain the model are presented. Finally, the model is linked to an evolutionary algorithm to optimize inductor performances.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116616817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Exploring design tradeoffs in analog IC placement with current-flow & current-density considerations 探索在电流和电流密度的考虑下模拟IC放置的设计权衡
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301697
R. Martins, R. Póvoa, N. Lourenço, N. Horta
{"title":"Exploring design tradeoffs in analog IC placement with current-flow & current-density considerations","authors":"R. Martins, R. Póvoa, N. Lourenço, N. Horta","doi":"10.1109/SMACD.2015.7301697","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301697","url":null,"abstract":"In this paper, the concept of hierarchical multi-objective optimization (MOO) is applied to analog integrated circuit (IC) placement automation, where current-flow and current-density considerations are taken to improve the reliability and, reduce the routing-induced parasitics of the circuit post-layout. The current-flow constraints are satisfied by forcing a monotonic routing directly in an absolute placement representation, while the impact of current-intensive interconnects is mitigated with the electromigration (EM)-aware optimization of the wiring topology (WT) for all nets of the circuit. The problem's complexity is reduced using the hierarchy in the circuit's partitions, combining, bottom-up, Pareto optimal fronts (POFs) of placements that explore the tradeoffs between the design objectives. The approach is demonstrated with post-layout results in an analog circuit structure for the UMC 130nm design process.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122390989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena 一种确定性老化模拟器及对老化现象具有鲁棒性的模拟电路尺寸测量工具
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301699
Engin Afacan, Gönenç Berkol, G. Dundar, A. E. Pusane, Faik Baskaya
{"title":"A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena","authors":"Engin Afacan, Gönenç Berkol, G. Dundar, A. E. Pusane, Faik Baskaya","doi":"10.1109/SMACD.2015.7301699","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301699","url":null,"abstract":"Analog circuit sizing has become a very challenging process due to increased non-idealities for advanced technology nodes. Moreover, reliability of circuits has become a major concern, where process variations and aging phenomena have been substantially worsened in deep-sub-micron devices. Thereby, traditional circuit optimization tools have been replaced by more complicated ones, which take reliability and variability issues into account. Efficient variability analysis and yield-aware circuit synthesis have been studied for many years, and numerous solutions have been proposed in the literature. On the other hand, aging analysis is still quite problematic in terms of accuracy and efficiency; therefore, more reliable and effective tools have emerged, especially for design automation systems. This study proposes an efficient deterministic aging simulator and an aging-aware analog circuit sizing tool.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128786572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A beam steering unit for active phased-array antennas based on FPGA synthesized delay-lines and PLLs 一种基于FPGA合成延迟线和锁相环的有源相控阵天线波束导向装置
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301709
G. D'Amato, G. Avitabile, G. Coviello, C. Talarico
{"title":"A beam steering unit for active phased-array antennas based on FPGA synthesized delay-lines and PLLs","authors":"G. D'Amato, G. Avitabile, G. Coviello, C. Talarico","doi":"10.1109/SMACD.2015.7301709","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301709","url":null,"abstract":"This paper introduces the design and implementation of a high performance, reconfigurable four channel beam steering unit (BSU) for active phased-array antennas based on FPGA synthesized delay-lines and PLLs. The unit allows a per channel programmable time delay equivalent to a phase shift tuning step of about 1.4°. A prototype has been implemented to validate the viability of the proposed approach across the 2.4-GHz industrial-scientific-medical (ISM) band.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115385290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A fast and accurate reliability simulation method for analog circuits 一种快速准确的模拟电路可靠性仿真方法
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301704
A. Toro-Frías, R. Castro-López, E. Roca, F. Fernández, J. Martín-Martínez, R. Rodríguez, M. Nafría
{"title":"A fast and accurate reliability simulation method for analog circuits","authors":"A. Toro-Frías, R. Castro-López, E. Roca, F. Fernández, J. Martín-Martínez, R. Rodríguez, M. Nafría","doi":"10.1109/SMACD.2015.7301704","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301704","url":null,"abstract":"Reliability has become a critical challenge in integrated circuit design in today's CMOS technologies. Aging problems have been added to the well-known issues due to spatial variations that are caused by imperfections in the fabrication process. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers (HC) cause a time-dependent variability that is added to the spatial variability. In addition, the BTI presents a stochastic behaviour, which may cause, for instance, time-varying mismatch. In this work, a model based on the physics of this phenomenon is implemented to accurately know its impact on the circuit performances. This method is focused on the analysis of analog circuits, taking into account the impact of both temporal and spatial variability. An effient simulation flow is implemented to evaluate the circuit performance at any instant of the circuit lifetime.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115240343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Grounded active inductors design optimization for fQmax = 14.2GHz using a 130 nm CMOS technology 基于130 nm CMOS技术的fQmax = 14.2GHz接地有源电感设计优化
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301693
M. Pandey, A. Canelas, R. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta
{"title":"Grounded active inductors design optimization for fQmax = 14.2GHz using a 130 nm CMOS technology","authors":"M. Pandey, A. Canelas, R. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta","doi":"10.1109/SMACD.2015.7301693","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301693","url":null,"abstract":"This paper presents a novel design of an active inductor based on the topology of Manetakis regulated cascode active inductor. The aim of this work is to enhance the manual design of active inductors by using AIDA-C design automation methodology. The circuit is manually designed using a 130 nm CMOS technology in Cadence® to obtain an Inductor operating at 14.2GHz. The sizing of the proposed active inductor has later been optimized using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool. The AIDA-C circuit sizing tool was able to achieve active inductor's solutions with higher quality factor, higher inductance at the operating frequency and also higher bandwidth than the manually designed solution, with the additional surplus of presenting a set of alternative Pareto optimal solutions that enables the designer to choose the most suitable circuit.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125486801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Mixed-signal test band guarding using digitally coded indirect measurements 使用数字编码间接测量的混合信号测试带保护
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301708
Álvaro Gómez-Pau, L. Balado, J. Figueras
{"title":"Mixed-signal test band guarding using digitally coded indirect measurements","authors":"Álvaro Gómez-Pau, L. Balado, J. Figueras","doi":"10.1109/SMACD.2015.7301708","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301708","url":null,"abstract":"Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information. In this work, the pass/fail test regions are encoded using octrees in the measure space. These octrees, generated in the training phase, will serve to cluster the forthcoming circuits in the production testing phase solely relying on indirect measurements. Also, a band guarding criterion is used to achieve the specified test targets in terms of test escapes and test yield loss metrics. The combined use of octree based encoding and specification band guarding makes the testing procedure fast and efficient. The proposed method has been applied to test a band-pass Biquad filter affected by parametric variations. Different scenarios have been studied and evaluated in the presence of noisy measurements. Promising simulation results are reported showing remarkable improvements when the band guarding criterion is used.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124893038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of IC package on radiated susceptibility of board level interconnection IC封装对板级互连辐射敏感性的影响
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301676
Fatemeh Vafaee Zonouz, N. Masoumi, M. Mehri
{"title":"Effect of IC package on radiated susceptibility of board level interconnection","authors":"Fatemeh Vafaee Zonouz, N. Masoumi, M. Mehri","doi":"10.1109/SMACD.2015.7301676","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301676","url":null,"abstract":"In this paper the effect of integrated circuit (IC) package on radiated susceptibility of board level interconnection is investigated. A closed form expression is derived for the induced voltage response of an IC pin in the frequency domain, which considered the loading effect of IC internal circuit and its package. The configuration is located on printed circuit board (PCB) exposed to an external electromagnetic field. Moreover, simulations have been done to verify the effect of package lead on susceptibility of IC. The influence of the wave frequency and the illumination angle on the amplitude of induced voltages is studied. The IC internal circuit and its package behave as a high pass filter. It attenuates the low frequency signals, but as frequency increases, the filter efficiency decreases.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123648161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A New CMOS four-quadrant analog multiplier with differential output 一种新型CMOS四象限差分模拟乘法器
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301684
A. N. Saatlo, Abolfazl Amiri, Loghman Asadpour
{"title":"A New CMOS four-quadrant analog multiplier with differential output","authors":"A. N. Saatlo, Abolfazl Amiri, Loghman Asadpour","doi":"10.1109/SMACD.2015.7301684","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301684","url":null,"abstract":"This paper presents a new four-quadrant analog multiplier circuit based on a new symmetrical configuration designed in CMOS technology. The proposed circuit is suitable for low voltage and low power applications. Compared to the corresponding already published works, the dynamic input and output ranges of the circuit are improved owing to the fact that the circuit works in the saturation region not in weak inversion. High accuracy is the further advantage of the circuit. In order to simulate the circuit, HSPICE simulator is utilized to verify the validity of the theoretical analysis in 0.18 μm CMOS technology, where under supply voltage of 1.5 V, the input range of the proposed circuit is ±400 mV, total power consumption is 44 μW, and the corresponding nonlinearity remains as low as 1.5 %. Moreover, the band-width of the circuit is found to be 196 MHz.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"340 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133923773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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