A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena

Analog circuit sizing has become a very challenging process due to increased non-idealities for advanced technology nodes. Moreover, reliability of circuits has become a major concern, where process variations and aging phenomena have been substantially worsened in deep-sub-micron devices. Thereby, traditional circuit optimization tools have been replaced by more complicated ones, which take reliability and variability issues into account. Efficient variability analysis and yield-aware circuit synthesis have been studied for many years, and numerous solutions have been proposed in the literature. On the other hand, aging analysis is still quite problematic in terms of accuracy and efficiency; therefore, more reliable and effective tools have emerged, especially for design automation systems. This study proposes an efficient deterministic aging simulator and an aging-aware analog circuit sizing tool.