A fast and accurate reliability simulation method for analog circuits

Reliability has become a critical challenge in integrated circuit design in today's CMOS technologies. Aging problems have been added to the well-known issues due to spatial variations that are caused by imperfections in the fabrication process. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers (HC) cause a time-dependent variability that is added to the spatial variability. In addition, the BTI presents a stochastic behaviour, which may cause, for instance, time-varying mismatch. In this work, a model based on the physics of this phenomenon is implemented to accurately know its impact on the circuit performances. This method is focused on the analysis of analog circuits, taking into account the impact of both temporal and spatial variability. An effient simulation flow is implemented to evaluate the circuit performance at any instant of the circuit lifetime.