{"title":"探索在电流和电流密度的考虑下模拟IC放置的设计权衡","authors":"R. Martins, R. Póvoa, N. Lourenço, N. Horta","doi":"10.1109/SMACD.2015.7301697","DOIUrl":null,"url":null,"abstract":"In this paper, the concept of hierarchical multi-objective optimization (MOO) is applied to analog integrated circuit (IC) placement automation, where current-flow and current-density considerations are taken to improve the reliability and, reduce the routing-induced parasitics of the circuit post-layout. The current-flow constraints are satisfied by forcing a monotonic routing directly in an absolute placement representation, while the impact of current-intensive interconnects is mitigated with the electromigration (EM)-aware optimization of the wiring topology (WT) for all nets of the circuit. The problem's complexity is reduced using the hierarchy in the circuit's partitions, combining, bottom-up, Pareto optimal fronts (POFs) of placements that explore the tradeoffs between the design objectives. The approach is demonstrated with post-layout results in an analog circuit structure for the UMC 130nm design process.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Exploring design tradeoffs in analog IC placement with current-flow & current-density considerations\",\"authors\":\"R. Martins, R. Póvoa, N. Lourenço, N. Horta\",\"doi\":\"10.1109/SMACD.2015.7301697\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the concept of hierarchical multi-objective optimization (MOO) is applied to analog integrated circuit (IC) placement automation, where current-flow and current-density considerations are taken to improve the reliability and, reduce the routing-induced parasitics of the circuit post-layout. The current-flow constraints are satisfied by forcing a monotonic routing directly in an absolute placement representation, while the impact of current-intensive interconnects is mitigated with the electromigration (EM)-aware optimization of the wiring topology (WT) for all nets of the circuit. The problem's complexity is reduced using the hierarchy in the circuit's partitions, combining, bottom-up, Pareto optimal fronts (POFs) of placements that explore the tradeoffs between the design objectives. The approach is demonstrated with post-layout results in an analog circuit structure for the UMC 130nm design process.\",\"PeriodicalId\":207878,\"journal\":{\"name\":\"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMACD.2015.7301697\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMACD.2015.7301697","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Exploring design tradeoffs in analog IC placement with current-flow & current-density considerations
In this paper, the concept of hierarchical multi-objective optimization (MOO) is applied to analog integrated circuit (IC) placement automation, where current-flow and current-density considerations are taken to improve the reliability and, reduce the routing-induced parasitics of the circuit post-layout. The current-flow constraints are satisfied by forcing a monotonic routing directly in an absolute placement representation, while the impact of current-intensive interconnects is mitigated with the electromigration (EM)-aware optimization of the wiring topology (WT) for all nets of the circuit. The problem's complexity is reduced using the hierarchy in the circuit's partitions, combining, bottom-up, Pareto optimal fronts (POFs) of placements that explore the tradeoffs between the design objectives. The approach is demonstrated with post-layout results in an analog circuit structure for the UMC 130nm design process.