{"title":"A causal reasoning-based approach for analog circuit verification","authors":"Fanshu Jiao, A. Doboli","doi":"10.1109/SMACD.2015.7301711","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301711","url":null,"abstract":"This paper proposes a novel analog circuit verification approach using causal reasoning. To verify analog circuits, the flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justification [1]. Then, topological structures corresponding to the starting ideas and design step sequences are verified individually by replacing the related devices with ideal amplifier model. Circuit performance is evaluated through Spectre simulation. Comparing simulation results reveals incorrect functional issues and/or performance drawbacks (negative causes) of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124470145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Theoretical framework for asynchronous feedback Network Under Balance (NUB)","authors":"G. Uygur, L. Gries, S. Sattler","doi":"10.1109/SMACD.2015.7301689","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301689","url":null,"abstract":"We propose a theoretical framework for the associative composition of functionally stable asynchronous feedback Networks Under Balance (NUB) for safety critical systems. It is totally closed under inversion and decomposition; thus, it can be applied to many applications embedded in asynchronous environment. For this, we engage our Automata Based Composition (ABC); the given network can now be interpreted as an asynchronous feedback, functionally stable automaton. As the ABC is invertible, it can be exhaustively used for issues of test and diagnosis based on a correct-by-construction paradigm. To demonstrate the practical application of the theory, we present our laboratory setup of the theoretical framework as a proof of concept by developing a set of boundary conditions which lead to an implementation in a further step. For this purpose, we build up a network of microcontroller boards and a set of specialized firmwares implementing the different components of the NUB.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125795672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Numerical method for ZVS investigation in isolated converters","authors":"G. Di Capua, N. Femia","doi":"10.1109/SMACD.2015.7301694","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301694","url":null,"abstract":"The effect of the parasitic paramete transformer and MOSFETs and their impa behavior and efficiency in ZVS isolated co effectively investigated by using the numerical m in this paper. This method helps in the valid achievement of the ZVS operation. A Low-Side Clamp converter is discussed as a case stud results prove the effectiveness of the proposed n in commutations analysis.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125831948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xin Huang, V. Sukharev, J. Choy, Hai-Bao Chen, E. Tlelo-Cuautle, S. Tan
{"title":"Full-chip electromigration assessment: Effect of cross-layout temperature and thermal stress distributions","authors":"Xin Huang, V. Sukharev, J. Choy, Hai-Bao Chen, E. Tlelo-Cuautle, S. Tan","doi":"10.1109/SMACD.2015.7301679","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301679","url":null,"abstract":"Many prior works have investigated electromigration (EM) on full-chip power grid interconnects, which has become one of major reliability concerns in nanometer VLSI design. However, most of the published results were obtained under the assumption of uniformly distributed temperature and/or residual stress across interconnects. In this paper, we demonstrate the implementation of novel methodology and flow for full-chip EM assessment on the multi-layered power grid networks of a 32nm test-chip and investigate the impacts of the within-die temperature and thermal stress variations on the failure rate. The proposed approach is based on recently developed physics-based EM models and the EM-induced IR-drop degradation criterion that replaces the traditional conservative weakest segment method. The cross-layout temperature distribution caused by power dissipations in devices and by interconnect Joule heating has been characterized and taken into account in the full-chip EM assessment methodology. Results of the simulations performed on the analyzed multi-layered power/ground nets show that traditional assumption of the uniform average temperature leads to inaccurate predictions of the time-to-failure (TTF). Furthermore, the consideration of thermal stress variation results in a retarded EM induced degradation.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129721420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integration of QMC based yield-aware pareto front techniques on MOEA/D for robust analog synthesis","authors":"Murat Pak, Francisco V. Fernández, G. Dundar","doi":"10.1109/SMACD.2015.7301705","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301705","url":null,"abstract":"This paper focuses on the implementation of different techniques for the integration of yield in the synthesis loop of analog ICs. Several algorithms have been developed for multi-objective optimization. Among these optimizers, MOEA/D (Multi-Objective Evolutionary Algorithm with Decomposition) is known as a powerful synthesizer. By using MOEA/D, some quality checks on practical designs have been realized in order to show the algorithm is well-suited for robust multi-objective optimization of analog circuits. Another issue that is considered is the inclusion of yield for obtaining robust PFs for analog sizing problems. Several techniques are discussed and three different yield-aware PF techniques have been implemented on MOEA/D. The implemented yield-aware PF techniques are compared by using a fully-differential folded-cascode amplifier. The results suggest that all three of these techniques look promising for high dimensional robust optimization of analog circuits.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"177 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113989083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wideband Distortion Contribution Analysis of analog circuits with differential signalling","authors":"A. Cooman, G. Vandersteen","doi":"10.1109/SMACD.2015.7301674","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301674","url":null,"abstract":"Distortion Contribution Analysis (DCA) is a simulation-based analysis in which the total output distortion generated by an analog electronic circuit is split into the contributions of each of its sub-circuits. Earlier work has shown that combining the Best Linear Approximation (BLA) with a classic noise analysis yields a DCA which uses a wideband excitation signal without requiring knowledge about the underlying technology. In this paper, the BLA-based DCA is augmented to be able to cope with circuits that use differential signalling. Transforming the Sparameters of the sub-circuits in the DCA into a representation that works on the differential and common-mode signals leads to distortion contributions which are easy to interpret when differential signals are present in the circuit. Additionally, an improved test is introduced to indicate the accuracy of the DCA.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123359869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Jassi, B. Bordes, Daniel Muller-Gritschneder, Ulf Schlichtmann
{"title":"Automation of FPGA performance monitoring and debugging Using IP-XACT and graph-grammars","authors":"M. Jassi, B. Bordes, Daniel Muller-Gritschneder, Ulf Schlichtmann","doi":"10.1109/SMACD.2015.7301702","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301702","url":null,"abstract":"Divide and conquer is already a proven strategy to handle the complexity of state-of-the-art SoCs. For any minor or major revision of an SoC, difficult decisions about its architecture have to be made at very early stages of the design cycle. System prototyping on FPGAs is an essential step in the SoC design flow for the verification of the hardware architecture. In this paper, we present a graph-grammar-based methodology to automate the FPGA prototyping for SoC performance monitoring and debugging analysis. Our work uses the IP-XACT description of vendor-specific hardware monitoring and debugging IPs for the target FPGA platform. Using graph-grammar principles the hardware monitors (HM) are automatically integrated into the host SoC architecture under consideration. Under the FPGA resource constraints, our tool splits the set of analysis tasks into multiple subsets, with each subset fitting into the available FPGA resources. The tool solves this as a classical bin packing problem. The tool then generates the SoC IP-XACT descriptions and the design descriptions for FPGA programming with integrated HMs for each new subset. The new SoCs are functionally equivalent to the original SoC.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124940728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A hybrid method for feature selection in the context of alternate test","authors":"G. Léger, M. Barragán","doi":"10.1109/SMACD.2015.7301707","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301707","url":null,"abstract":"Machine-learning test strategy has been developed in the last decade as an alternative to costly specification-driven tests for Analog, Mixed-Signal and RF circuits (AMS-RF). The concept is simple: powerful algorithms are used to map simple measurements onto specifications. But the proper execution requires an information-rich input space. This paper presents an efficient hybrid algorithm to select the best subset of signatures (or features) among a large number of candidates and shows how it can be applied to eventually propose the development of new ones.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125973465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"NBTI-aware bit line voltage control with boosted supply voltage for improvement of 6T SRAM cell read stability","authors":"","doi":"10.1109/smacd.2015.7301691","DOIUrl":"https://doi.org/10.1109/smacd.2015.7301691","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) is one of the degradation phenomena that reduces the circuit reliability in immensely scaled CMOS technologies. In this work, effects of NBTI have been examined on a single PMOS transistor and further on SRAM operations. It has been observed that read Static Noise Margin (SNM) of the 6T SRAM cell degrades due to NBTI. To compensate this degradation different approaches have been reported previously. One of the approach is boosted power supply, but it leads to larger Read Power. The other approach is bit line voltage control, which reduces speed of read operation. Both of these approaches result in degradation of other performance parameters while improving SNM. In this paper, a new optimized method is proposed which is a hybrid model of both boosted power supply and bit line voltage control approach. First we develop an analytical model for SNM calculation as a function of change in threshold voltage (△Vtp) due to NBTI. Further models are developed for increased value of supply voltage and decreased value of bit line voltage as a function of △Vtp. These models are used to develop hybrid model for NBTI compensation. The simulated results show that proposed model do not degrade power dissipation and speed after compensating the NBTI effect. Our proposed model results in the optimized values of Read Power (PREAD = 12.28nW) and Read Current (IREAD = 15.75nA) that are in close agreement with the values (PREAD = 13.59nW, IREAD = 15.50nA) when no NBTI effect was present in the circuit.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128340279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}