NBTI-aware bit line voltage control with boosted supply voltage for improvement of 6T SRAM cell read stability

Negative Bias Temperature Instability (NBTI) is one of the degradation phenomena that reduces the circuit reliability in immensely scaled CMOS technologies. In this work, effects of NBTI have been examined on a single PMOS transistor and further on SRAM operations. It has been observed that read Static Noise Margin (SNM) of the 6T SRAM cell degrades due to NBTI. To compensate this degradation different approaches have been reported previously. One of the approach is boosted power supply, but it leads to larger Read Power. The other approach is bit line voltage control, which reduces speed of read operation. Both of these approaches result in degradation of other performance parameters while improving SNM. In this paper, a new optimized method is proposed which is a hybrid model of both boosted power supply and bit line voltage control approach. First we develop an analytical model for SNM calculation as a function of change in threshold voltage (△Vtp) due to NBTI. Further models are developed for increased value of supply voltage and decreased value of bit line voltage as a function of △Vtp. These models are used to develop hybrid model for NBTI compensation. The simulated results show that proposed model do not degrade power dissipation and speed after compensating the NBTI effect. Our proposed model results in the optimized values of Read Power (PREAD = 12.28nW) and Read Current (IREAD = 15.75nA) that are in close agreement with the values (PREAD = 13.59nW, IREAD = 15.50nA) when no NBTI effect was present in the circuit.