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2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)最新文献

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A new simulation program for analog circuits using symbolic analysis techniques 一个新的模拟电路仿真程序，使用符号分析技术
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301682
Giuseppe Fontana, F. Grasso, A. Luchetta, S. Manetti, M. C. Piccirilli, A. Reatti
{"title":"A new simulation program for analog circuits using symbolic analysis techniques","authors":"Giuseppe Fontana, F. Grasso, A. Luchetta, S. Manetti, M. C. Piccirilli, A. Reatti","doi":"10.1109/SMACD.2015.7301682","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301682","url":null,"abstract":"The main capabilities and the possible applications of a software package, developed by the authors and aimed at the simulation of analog linear (or linearized) circuits, are presented in this paper. The program, named SapWin 4.0, is an enhancement of a previous software package of the same authors developed along the last two decades and distributed in many schools, institutions, industries and research centers for different purposes. It is based on the use of symbolic analysis techniques and the main application fields are the analysis, design and teaching areas of Electrical Engineering. The suggestions and corrections received from the different users all over the world have been collected to generate a completely renewed software, that could become an efficient tool in the field of analog circuits, also filling the typical gaps of classical numerical simulators.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128417828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A configurable pulse generator for intermittent operation and synchronization of IR-UWB receivers 一种可配置的脉冲发生器，用于IR-UWB接收机的间歇操作和同步
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301695
O. Z. Batur, G. Dundar, M. Koca
{"title":"A configurable pulse generator for intermittent operation and synchronization of IR-UWB receivers","authors":"O. Z. Batur, G. Dundar, M. Koca","doi":"10.1109/SMACD.2015.7301695","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301695","url":null,"abstract":"In this paper, we present a low power and configurable pulse generator with on-off keying (OOK) modulator feature for non-coherent impulse radio (IR) receiver synchronization and intermittent receiver operation. The pulse generator has adjustable pulse width and pulse delay properties. The configurability is achieved using on-chip bias cells with external inputs. The pulse width can be configured between 2 ns and 15 ns, and pulse delay can be adjusted up to 6 ns at 1.2 V supply voltage. The dynamic energy consumption per pulse (Epp) of the mono-pulse generator is 48 pJ/pulse and 30 pJ/pulse at 1.2 V and 0.6 V supply voltages, respectively. 250 MHz pulse repetition frequency (PRF) is observed in the measurements.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129884696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation AIDA:模拟ic的鲁棒布局感知合成，包括尺寸和布局生成
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301703
R. Martins, N. Lourenço, A. Canelas, R. Póvoa, N. Horta
{"title":"AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation","authors":"R. Martins, N. Lourenço, A. Canelas, R. Póvoa, N. Horta","doi":"10.1109/SMACD.2015.7301703","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301703","url":null,"abstract":"This paper presents AIDA 2015, the newest version of AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the AIDA environment, www.aidasoft.com, is demonstrated for analog IC design, sizing and layout generation, using state-of-the-art technologies, and validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO ®, or CALIBRE®.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133198214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Improved numerical modal technique for fast and accurate modeling of transmission planar structures: Application to microstrip line 改进的传输平面结构快速准确建模的数值模态技术:在微带线上的应用
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301687
A. Khodja, M. Yagoub, R. Touhami, H. Baudrand
{"title":"Improved numerical modal technique for fast and accurate modeling of transmission planar structures: Application to microstrip line","authors":"A. Khodja, M. Yagoub, R. Touhami, H. Baudrand","doi":"10.1109/SMACD.2015.7301687","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301687","url":null,"abstract":"This paper highlights a fast and accurate full-wave modal integral technique based on the calculation of inner products obtained through the Galerkin's procedure, when trial functions taken in the account the edge effects are used. By using trapezoidal numerical integration with nonuniform discretization steps, the proposed approach allows fast calculation of such inner products, thus significantly reducing the required CPU-time for microstrip-type structure analysis. The efficiency of the proposed technique is demonstrated through a successful comparison of the dispersion characteristics to published data.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133231872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Crosstalk noise analysis for unequal length interconnects on PCBs using length dependent parameters 利用长度相关参数分析pcb上不等长度互连的串扰噪声
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301692
Kanan Sehat, N. Masoumi
{"title":"Crosstalk noise analysis for unequal length interconnects on PCBs using length dependent parameters","authors":"Kanan Sehat, N. Masoumi","doi":"10.1109/SMACD.2015.7301692","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301692","url":null,"abstract":"In this paper the crosstalk noise in parallel traces is investigated; in order to approach this propose, two different RLC models are used. These models are applied to two traces which are parallel and are not equal in length. These two models are different in the value of the resistances, inductances and capacitances. In the first case, the equivalent RLC model is used. In other words, the value of the RLCs are equal in all segments in the first case that is named the conventional model. The second case is the RLC non-equivalent model (segmented model with un-equal RLCs). In each of these two cases, we use three segments for simulations and the S-Parameters of the traces are extracted in order to study the accuracy of the models. Finally the results are compared with the full wave simulations and it is shown that the RLC non-equivalent model is more accurate in comparison with the equivalent model.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130856369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A broadband high linearity inductorless CMOS variable gain amplifier for square kilometer array 一种用于平方公里阵列的宽带高线性度无电感CMOS变增益放大器
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301683
I. Abdalla, A. Allam, H. Jia, Ramesh K. Pokharel
{"title":"A broadband high linearity inductorless CMOS variable gain amplifier for square kilometer array","authors":"I. Abdalla, A. Allam, H. Jia, Ramesh K. Pokharel","doi":"10.1109/SMACD.2015.7301683","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301683","url":null,"abstract":"This paper presents a high-bandwidth 2 GHz CMOS variable gain amplifier (VGA) for using in the band of square kilometer array (SKA) range that achieves an 18 dB dynamic range (DR) while powered from a single 1.8 V supply. This VGA capability is obtained by employing a passive digital T-bridge attenuator followed by a fixed amplifier, the use of attenuator in the front end of the VGA results in a high linearity of 28 dBm to 34 dBm over the full DR. In contrast to traditional VGAs [5], [6], the VGA exhibits 30-50 dB more in DR while its bandwidth and IP3 extends below the presented.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115746822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the use of signal modelling techniques for simulating 1/ fβ -noise 利用信号建模技术模拟1/ fβ噪声
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301678
Y. Ferdi, Mohamed Reda Lakehal, A. Taleb-Ahmed
{"title":"On the use of signal modelling techniques for simulating 1/ fβ -noise","authors":"Y. Ferdi, Mohamed Reda Lakehal, A. Taleb-Ahmed","doi":"10.1109/SMACD.2015.7301678","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301678","url":null,"abstract":"This paper presents a comparison study between various signal modeling techniques, combined with power series expansion to design infinite impulse response (IIR) filters based on fractional integration for 1/fβ sequences synthesis. It was found that the approximation accuracy of the power spectra, the computation time and the space memory required depend highly on the signal modeling techniques used. Best results were obtained using iterative technique. The burden of time consumption and space memory required are lowered by introducing impulse invariance based method.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115824638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
All-digital phase locked loop design assistant 全数字锁相环设计助手
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301710
Yalcin Balcioglu, G. Dundar
{"title":"All-digital phase locked loop design assistant","authors":"Yalcin Balcioglu, G. Dundar","doi":"10.1109/SMACD.2015.7301710","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301710","url":null,"abstract":"An All-Digital Integer-N Phase Locked Loop (ADPLL) design assistant that models all the sub-blocks and noise sources in phase domain has been developed. For chosen top level design parameters, the generator designs the desired closed loop, open loop and digital loop filter characteristics of the ADPLL and analyzes the resulting phase noise performance of the loop.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128919857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low cost and simple fluxgate magnetometer implementation 一种低成本、简单的磁通门磁强计实现
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301685
S. Tanriseven, H. Can, U. Topal, C. Birlikseven, R. Vural
{"title":"A low cost and simple fluxgate magnetometer implementation","authors":"S. Tanriseven, H. Can, U. Topal, C. Birlikseven, R. Vural","doi":"10.1109/SMACD.2015.7301685","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301685","url":null,"abstract":"Having wide application area and high performance, Fluxgate magnetometers are popular devices to measure low frequency AC and DC magnetic field vectors. In this work, we designed a simple and a low cost magnetometer prototype to obtain natural earth magnetic field value between ± 0.6 Gauss (G). Using basic microprocessors and a phase detection code technique, unlike conventionally lock-in amplifier, we drove the sensor by excitation signal whose frequency is 1.086 kHz and magnitude is 31 mA. Eventually, the direction and the magnitude of DC magnetic field is successfully determined with the implemented fluxgate magnetometer prototype.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132471006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis 为提高并行模拟集成电路合成效率而安排评估任务
2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI: 10.1109/SMACD.2015.7301700
David Neves, N. Lourenço, N. Horta
{"title":"Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis","authors":"David Neves, N. Lourenço, N. Horta","doi":"10.1109/SMACD.2015.7301700","DOIUrl":"https://doi.org/10.1109/SMACD.2015.7301700","url":null,"abstract":"This paper presents a methodology to increase the efficiency of automatic analog integrated circuit synthesis and optimization including simultaneously sizing; layout; and worst case corners, by using the multiple CPUs that are cheaply available in today's workstations. While most individual tools, for example circuit simulators already provide some sort of multi-processor capability, the efficiency of holistic solutions that incorporate both the sizing, layout, parasitic extraction and worst case performance evaluation can be further extended by proper use of the available computational resources. Moreover, due to licensing costs, the number of instances of each tool is usually limited. By efficiently scheduling the synthesis tasks over the available processing elements, these scarce resources (licenses) are used optimally. The proposed approach was verified with the evaluation flow of AIDA, for the simultaneous layout and worst case corner aware synthesis of a typical analog circuit showing an improvement of about 20% in processing time when compared to the trivial parallelization.","PeriodicalId":207878,"journal":{"name":"2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126454931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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