全数字锁相环设计助手

2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI:10.1109/SMACD.2015.7301710

Yalcin Balcioglu, G. Dundar

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引用次数: 0

摘要

开发了一种全数字整数n锁相环(ADPLL)设计助手，可以在相域中对所有子块和噪声源进行建模。对于选定的顶层设计参数，发生器设计出所需的ADPLL的闭环、开环和数字环滤波器特性，并分析由此产生的环路相位噪声性能。

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All-digital phase locked loop design assistant

An All-Digital Integer-N Phase Locked Loop (ADPLL) design assistant that models all the sub-blocks and noise sources in phase domain has been developed. For chosen top level design parameters, the generator designs the desired closed loop, open loop and digital loop filter characteristics of the ADPLL and analyzes the resulting phase noise performance of the loop.

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来源期刊

2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

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