A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena

2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2015-10-26 DOI:10.1109/SMACD.2015.7301699

Engin Afacan, Gönenç Berkol, G. Dundar, A. E. Pusane, Faik Baskaya

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引用次数: 15

Abstract

Analog circuit sizing has become a very challenging process due to increased non-idealities for advanced technology nodes. Moreover, reliability of circuits has become a major concern, where process variations and aging phenomena have been substantially worsened in deep-sub-micron devices. Thereby, traditional circuit optimization tools have been replaced by more complicated ones, which take reliability and variability issues into account. Efficient variability analysis and yield-aware circuit synthesis have been studied for many years, and numerous solutions have been proposed in the literature. On the other hand, aging analysis is still quite problematic in terms of accuracy and efficiency; therefore, more reliable and effective tools have emerged, especially for design automation systems. This study proposes an efficient deterministic aging simulator and an aging-aware analog circuit sizing tool.

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一种确定性老化模拟器及对老化现象具有鲁棒性的模拟电路尺寸测量工具

由于先进技术节点的非理想性增加，模拟电路的尺寸已成为一个非常具有挑战性的过程。此外，电路的可靠性已成为一个主要问题，在深亚微米器件中，工艺变化和老化现象已经大大恶化。因此，传统的电路优化工具已经被更复杂的工具所取代，这些工具考虑了可靠性和可变性问题。有效的变异性分析和产率感知电路的合成已经研究了多年，并且在文献中提出了许多解决方案。另一方面，老化分析在准确性和效率方面仍然存在很大问题;因此，出现了更可靠和有效的工具，特别是设计自动化系统。本研究提出一种高效的确定性老化模拟器及老化感知模拟电路尺寸测量工具。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

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