发布求助
文献互助 智能选刊 最新文献

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)最新文献

筛选
英文 中文
FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit FLOVA:一个带有SIMD指令和光照加速单元的四问题VLIW几何处理器
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852728
S. Nam, Byoung-Woon Kim, Y. Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, C. Kyung
{"title":"FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit","authors":"S. Nam, Byoung-Woon Kim, Y. Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, C. Kyung","doi":"10.1109/CICC.2000.852728","DOIUrl":"https://doi.org/10.1109/CICC.2000.852728","url":null,"abstract":"This paper describes a VLIW (very long instruction word) geometry processor called FLOVA (FLOating-Point VLIW Architecture) which was developed to accelerate the geometry stage of 3D graphics. FLOVA executes four instructions in one cycle and supports 136 instructions including 35 SIMD (single instruction multiple data) instructions to accelerate the geometry stage. Special features to accelerate transformation and lighting operations in 3D graphics geometry stage are described. FLOVA can calculate the power value of two floating-point numbers in only four clock cycles with a negligible loss of accuracy, compared to over 150 clock cycles in other processors.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91087961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Cypress Delta39K/sup TM/. A memory-rich, high performance, scalable CPLD architecture Cypress Delta39K/sup TM/。一个内存丰富，高性能，可扩展的CPLD架构
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852634
A. Kennings, H. Mohammed, J. P. Skudlarek, Binghe Tian
{"title":"Cypress Delta39K/sup TM/. A memory-rich, high performance, scalable CPLD architecture","authors":"A. Kennings, H. Mohammed, J. P. Skudlarek, Binghe Tian","doi":"10.1109/CICC.2000.852634","DOIUrl":"https://doi.org/10.1109/CICC.2000.852634","url":null,"abstract":"The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the Warp/sup TM/ 6.0 software.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84188183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.2 V, 433 MHz, 10 dBm, 38% global efficiency FSK transmitter integrated in a standard digital CMOS process 一个1.2 V, 433 MHz, 10 dBm, 38%全局效率的FSK发射机集成在一个标准的数字CMOS工艺
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852644
T. Melly, Alain-Serge Porret, C. Enz, E. Vittoz
{"title":"A 1.2 V, 433 MHz, 10 dBm, 38% global efficiency FSK transmitter integrated in a standard digital CMOS process","authors":"T. Melly, Alain-Serge Porret, C. Enz, E. Vittoz","doi":"10.1109/CICC.2000.852644","DOIUrl":"https://doi.org/10.1109/CICC.2000.852644","url":null,"abstract":"This paper describes the design of an FSK transmitter for the 433 MHz ISM (Industrial, Scientific, Medical) band, which is realized in a standard digital 0.5 /spl mu/m CMOS technology. It includes the PA itself, an upconverter, and the circuit generating the baseband quadrature signals with a continuous phase modulation. The overall measured efficiency of the packaged circuit is higher than 38% for a 1.2 V supply and an output power reaching 10 dBm at 433 MHz.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88368295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 300 K-gate 0.5 /spl mu/m CMOS implementation of an 8-VSB receiver IC [for HDTV] 300 k门0.5 /spl mu/m CMOS实现的8-VSB接收机IC[用于高清电视]
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852656
Ealwan Lee, Dongkyun Kim, Seokjun Lee, K. Kwon, Jongdae Kim, In-Cheol Kim, Yongho Kim, Sungju Park, Cheongon Kim, Haeryun Jung, Gyu-Hwan Chang
{"title":"A 300 K-gate 0.5 /spl mu/m CMOS implementation of an 8-VSB receiver IC [for HDTV]","authors":"Ealwan Lee, Dongkyun Kim, Seokjun Lee, K. Kwon, Jongdae Kim, In-Cheol Kim, Yongho Kim, Sungju Park, Cheongon Kim, Haeryun Jung, Gyu-Hwan Chang","doi":"10.1109/CICC.2000.852656","DOIUrl":"https://doi.org/10.1109/CICC.2000.852656","url":null,"abstract":"This paper presents an integrated 8-VSB receiver IC which demodulates and decodes the ATSC-compliant terrestrial RF transmission signal. The design has been accomplished in an ASIC-vendor independent way using only HDL description and synthesis tools. It can receive any IF signal of 5.38 MHz or 44 MHz. The chip has been implemented with equivalent 300 k gates comprising 200 k logic parts and 100 k gate-equivalent memory parts in an area of 8.0/spl times/7.7 mm/sup 2/. The chip is operative at 50 MHz and consumes approximately 3.2 W under 5 volts in a commercial operating condition.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87064634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SRAM embedded memory with low cost, flash EEPROM-switch-controlled redundancy SRAM嵌入式存储器，低成本，闪存eeprom开关控制冗余
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852668
R. McPartland, D. Loeper, F. Higgins, Raj Singh, G. MacDonald, G. Komoriya, S. Aymeloglu, M. DePaolis, C. Leung
{"title":"SRAM embedded memory with low cost, flash EEPROM-switch-controlled redundancy","authors":"R. McPartland, D. Loeper, F. Higgins, Raj Singh, G. MacDonald, G. Komoriya, S. Aymeloglu, M. DePaolis, C. Leung","doi":"10.1109/CICC.2000.852668","DOIUrl":"https://doi.org/10.1109/CICC.2000.852668","url":null,"abstract":"This paper describes the use of low cost, flash EEPROM switches to control redundancy in SRAM embedded memories. Flash cell design, operation and process technology are described. A 768K-bit embedded SRAM memory with flash controlled column redundancy and built in self-repair is presented.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86321630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
CMOS in the new millennium 新千年的CMOS
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852616
T. Ning
{"title":"CMOS in the new millennium","authors":"T. Ning","doi":"10.1109/CICC.2000.852616","DOIUrl":"https://doi.org/10.1109/CICC.2000.852616","url":null,"abstract":"The VLSI industry is accelerating towards the end of scaling (bulk) CMOS. Near its scaling limit, a CMOS transistor could have a channel length of about 25 nm, a switching speed about three times as fast as a device of 100-nm channel length, and an f/sub T/ of about 250 GHz. However realization of this CMOS technology is far from certain due to the many technical difficulties that must be overcome. In the next few years, while the application of CMOS to RF will grow rapidly, performance of digital CMOS will saturate. While development towards 25-nm channel length will continue, CMOS development will also be focused on opportunities beyond scaling the bulk device.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86354273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A versatile low-power power line FSK transceiver 多功能低功率电力线FSK收发器
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852677
R. Cappelletti, A. Baschirotto
{"title":"A versatile low-power power line FSK transceiver","authors":"R. Cappelletti, A. Baschirotto","doi":"10.1109/CICC.2000.852677","DOIUrl":"https://doi.org/10.1109/CICC.2000.852677","url":null,"abstract":"A versatile low-power half-duplex FSK transceiver for power line communication network applications is presented. The proposed power-line modem (PLM) satisfies the requirement of several protocols for both power-line communications and home automation applications. The device operation is fully controlled and programmed through an internal 24 bit register. It operates from a single 9 V supply (5 V is possible if no power delivery is required). During transmission, the PLM is able to deliver 1 W on 16 /spl Omega/, while during reception if dissipates only 3.5 mA. The PLM is realized in a 0.6 /spl mu/m BCD technology.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83601014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High-performance flexible all-digital quadrature up and down converter chip 高性能柔性全数字正交上下转换芯片
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852615
R. Pasko, L. Rijnders, P. Schaumont, S. Vernalde, D. Durackova
{"title":"High-performance flexible all-digital quadrature up and down converter chip","authors":"R. Pasko, L. Rijnders, P. Schaumont, S. Vernalde, D. Durackova","doi":"10.1109/CICC.2000.852615","DOIUrl":"https://doi.org/10.1109/CICC.2000.852615","url":null,"abstract":"In this paper, the design of an all-digital quadrature up and down converter with high accuracy and flexible IF settings is presented. The signal up/downconversion is achieved by interpolation/decimation combined with a programmable anti-alias filter preserving the selected frequency band during the sample rate conversion. This way a high-speed solution with low-power consumption is achieved. We used a novel technique to implement flexible IF settings. The resulting structure is capable of handling signals up to 160 MSPS and is suitable for coaxial access network modem applications.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89487730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Low power bus coding techniques considering inter-wire capacitances 考虑线间电容的低功耗总线编码技术
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852719
P. Sotiriadis, A. Chandrakasan
{"title":"Low power bus coding techniques considering inter-wire capacitances","authors":"P. Sotiriadis, A. Chandrakasan","doi":"10.1109/CICC.2000.852719","DOIUrl":"https://doi.org/10.1109/CICC.2000.852719","url":null,"abstract":"The power dissipation associated with driving data buses can be significant, especially considering the increasing component of inter-wire capacitance. Previous work on bus encoding has focused on minimizing transitions to reduce power dissipation. In this paper, it is shown that transition reduction is not necessarily the best approach for reducing power when the effects of inter-wire capacitance are considered. An electrical model for data buses designed with submicron technologies is presented and a family of coding techniques is proposed that can reduce the average power consumption of the bus by 40%.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78597585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 156
A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire 4分路125兆赫混合信号回波消除器，用于千兆以太网铜线
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI: 10.1109/CICC.2000.852708
Tai-Cheng Lee, B. Razavi
{"title":"A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire","authors":"Tai-Cheng Lee, B. Razavi","doi":"10.1109/CICC.2000.852708","DOIUrl":"https://doi.org/10.1109/CICC.2000.852708","url":null,"abstract":"A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers by 50 taps. Designed in a 0.4 /spl mu/m CMOS technology, the circuit employs an LMS algorithm to adapt to the cable length and impedance discontinuities, providing an echo suppression of 10 dB. The design operates at 125 MHz while consuming 43 mW from a 3 V supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76594278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信