Cypress Delta39K/sup TM/。一个内存丰富,高性能,可扩展的CPLD架构

A. Kennings, H. Mohammed, J. P. Skudlarek, Binghe Tian
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引用次数: 0

摘要

介绍了Cypress Delta39K CPLD系列的体系结构,包括:(i)分层结构;(ii)新颖的单源、专用轨道基于mux的路由架构;(三)大量的片上专用存储器。描述了包括宏单元、I/O单元和PLL函数在内的其他基本元素。最后,我们说明了使用Warp/sup TM/ 6.0软件可以将逻辑安装到代表性设备中的速度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Cypress Delta39K/sup TM/. A memory-rich, high performance, scalable CPLD architecture
The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the Warp/sup TM/ 6.0 software.
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