Cypress Delta39K/sup TM/. A memory-rich, high performance, scalable CPLD architecture

Abstract

The architecture of the Cypress Delta39K CPLD family is described, including: (i) the hierarchical organization; (ii) the novel single source, dedicated track MUX-based routing architecture; and (iii) the large quantity of on-chip specialty memory. Other essential elements including macrocells, I/O cells and PLL functions are described. Finally, we illustrate the speed with which logic can be fitted into a representative device using the Warp/sup TM/ 6.0 software.