具有622 MHz I/O接口的百万门PLD,多个pll和高性能嵌入式CAM

Sammy Cheung, Kar Keng Chua, B. Ang, Thow Pang Chong, Wei Lian Goay, Wei-Yee Koay, Sin Wo Kuan, Chooi Pei Lim, Jiunn Shyong Oon, Theam Thye See, C. Sung, Kim Pin Tan, Yu Fong Tan, C. K. Wong
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引用次数: 1

摘要

讨论了一种用于高性能系统集成的百万门可编程逻辑器件(PLD)。APEX 20K1000E采用0.18 /spl mu/m CMOS工艺制造。该芯片支持多种I/O标准,采用集成的LVDS (low voltage differential signaling)接口时,数据带宽可达622 Mbps。多个片上锁相环(PLL)提高性能并提供时钟频率合成。嵌入式内容可寻址内存(CAM)增强了快速搜索应用程序的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM
A million gate programmable logic device (PLD) designed for high performance system integration is discussed. The APEX 20K1000E is fabricated on a 0.18 /spl mu/m CMOS process. The chip supports multiple I/O standards with data bandwidth up to 622 Mbps when using the integrated low voltage differential signaling (LVDS) interfaces. Multiple on-chip phase-locked loops (PLL) increase performance and provide clock-frequency synthesis. The embedded content addressable memory (CAM) enhances performance for fast search applications.
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