Design methodology of the embedded DRAM with the virtual socket architecture

Abstract

This paper proposes the virtual socket architecture in order to reduce the design turn around time (TAT) of the embedded DRAM. By using the proposed architecture, the DRAM control circuitry is provided as the software macro to take advantage of the automated tools based on the synchronous circuit design. With array generator technology, this architecture can achieve high quality, quick turn around time (QTAT) flexible eDRAM design almost the same as the CMOS ASIC. We applied this virtual socket architecture to the 0.18 /spl mu/m embedded DRAM test device and confirmed over 166 MHz operation.