Ealwan Lee, Dongkyun Kim, Seokjun Lee, K. Kwon, Jongdae Kim, In-Cheol Kim, Yongho Kim, Sungju Park, Cheongon Kim, Haeryun Jung, Gyu-Hwan Chang
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A 300 K-gate 0.5 /spl mu/m CMOS implementation of an 8-VSB receiver IC [for HDTV]
This paper presents an integrated 8-VSB receiver IC which demodulates and decodes the ATSC-compliant terrestrial RF transmission signal. The design has been accomplished in an ASIC-vendor independent way using only HDL description and synthesis tools. It can receive any IF signal of 5.38 MHz or 44 MHz. The chip has been implemented with equivalent 300 k gates comprising 200 k logic parts and 100 k gate-equivalent memory parts in an area of 8.0/spl times/7.7 mm/sup 2/. The chip is operative at 50 MHz and consumes approximately 3.2 W under 5 volts in a commercial operating condition.