300 k门0.5 /spl mu/m CMOS实现的8-VSB接收机IC[用于高清电视]

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852656

Ealwan Lee, Dongkyun Kim, Seokjun Lee, K. Kwon, Jongdae Kim, In-Cheol Kim, Yongho Kim, Sungju Park, Cheongon Kim, Haeryun Jung, Gyu-Hwan Chang

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引用次数: 0

摘要

本文设计了一种集成的8-VSB接收芯片，用于对atsc标准的地面射频发射信号进行解调和解码。该设计以独立于asic厂商的方式完成，仅使用HDL描述和合成工具。它可以接收任何5.38 MHz或44 MHz的中频信号。该芯片已经实现了等效300 k门，包括200 k逻辑部件和100 k门等效存储器部件，面积为8.0/spl倍/7.7 mm/sup 2/。该芯片的工作频率为50 MHz，在商业工作条件下，功耗约为3.2 W，电压为5伏。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 300 K-gate 0.5 /spl mu/m CMOS implementation of an 8-VSB receiver IC [for HDTV]

This paper presents an integrated 8-VSB receiver IC which demodulates and decodes the ATSC-compliant terrestrial RF transmission signal. The design has been accomplished in an ASIC-vendor independent way using only HDL description and synthesis tools. It can receive any IF signal of 5.38 MHz or 44 MHz. The chip has been implemented with equivalent 300 k gates comprising 200 k logic parts and 100 k gate-equivalent memory parts in an area of 8.0/spl times/7.7 mm/sup 2/. The chip is operative at 50 MHz and consumes approximately 3.2 W under 5 volts in a commercial operating condition.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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