基于虚拟套接字架构的嵌入式DRAM设计方法

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852664

T. Yamauchi, M. Kinoshita, T. Amano, K. Dosaka, K. Arimoto, H. Ozaki, M. Yamada, T. Yoshihara

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引用次数: 4

摘要

为了缩短嵌入式DRAM的设计周转时间，提出了虚拟套接字结构。采用所提出的体系结构，将DRAM控制电路作为软件宏提供，以利用基于同步电路设计的自动化工具。采用阵列发生器技术，该架构可以实现与CMOS ASIC几乎相同的高质量，快速周转时间(QTAT)灵活的eDRAM设计。我们将这种虚拟插座架构应用于0.18 /spl mu/m嵌入式DRAM测试设备，并确认了超过166 MHz的操作。

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Design methodology of the embedded DRAM with the virtual socket architecture

This paper proposes the virtual socket architecture in order to reduce the design turn around time (TAT) of the embedded DRAM. By using the proposed architecture, the DRAM control circuitry is provided as the software macro to take advantage of the automated tools based on the synchronous circuit design. With array generator technology, this architecture can achieve high quality, quick turn around time (QTAT) flexible eDRAM design almost the same as the CMOS ASIC. We applied this virtual socket architecture to the 0.18 /spl mu/m embedded DRAM test device and confirmed over 166 MHz operation.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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