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[Proceedings] EURO ASIC `90最新文献

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Crosspoint element: Elemento de Cruce (EC) 交叉点元素:交叉点元素(EC)
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207930
A. Altadill, I. Carretero, M. Escudero, P. Mateos
{"title":"Crosspoint element: Elemento de Cruce (EC)","authors":"A. Altadill, I. Carretero, M. Escudero, P. Mateos","doi":"10.1109/EASIC.1990.207930","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207930","url":null,"abstract":"The VLSI integrated circuit \"Elemento de Cruce\" (EC) has been conceived as a multifunction device. The EC has been designed to work as the crosspoint element in a broadband (ATM) asynchronous transfer mode (ATM) switch block, as well as an interfacing device between a microprocessor, a codec or, in general, any data source and the ATM switch network. The EC works at a frequency of 43.75 MHz using a 16 bit parallel data format, giving a throughput of 700 Mbs. The chip is implemented with 13 K CMOS gates, 4 kbits of RAM memory and 25.5 kbits of FIFO memory. The IC is manufactured in 1.25 mu m twin-tub double metal level standard cell CMOS technology and has dimensions of 400 mils*400 mils, with nominal power dissipation of 1.3 W.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127031914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Global routing driven floorplanning 全局路由驱动的楼层规划
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207942
A. Herrigel
{"title":"Global routing driven floorplanning","authors":"A. Herrigel","doi":"10.1109/EASIC.1990.207942","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207942","url":null,"abstract":"A novel global routing driven floorplanning approach is presented. Rectangular cells such as in macrocell design are considered. The major contributions of the paper are: (1) a new model for the prediction of shape functions which enables one to consider a more general class of floorplan representations. (2) An improved two-dimensional partitioning procedure. (3) A dynamic updating scheme that considers interconnect area around each cell during the floorplan assembly. The technique supports a global perspective and considers simultaneously different design goals. An analytic-based optimization technique is applied for port allocation. Experimental results from industrial examples with many irregular cells show a considerable improvement over previous attempts.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121827795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A design planner including a fast predictive floorplanning tool 一个设计规划师，包括一个快速预测的地板规划工具
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207941
E. Chotin, A. Mignotte, G. Saucier
{"title":"A design planner including a fast predictive floorplanning tool","authors":"E. Chotin, A. Mignotte, G. Saucier","doi":"10.1109/EASIC.1990.207941","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207941","url":null,"abstract":"The design planner presented in this paper starts from a description of a circuit in terms of interconnected blocks which may be hard blocks (macrocells in a library, generated blocks like RAMs, PLAs) or soft blocks usually generated by synthesis tools. The design planner predicts the cost of a circuit in terms of area, yield and other issues (power, consumption, packaging), according to different technologies. A special attention is given to a fast accurate floorplanning prediction. Experiments on real circuits showed a good prediction accuracy.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124728604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
OASIS: a silicon compiler for semi-custom design OASIS:用于半定制设计的硅编译器
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207905
G. Kedem, F. Brglez, K. Kozminski
{"title":"OASIS: a silicon compiler for semi-custom design","authors":"G. Kedem, F. Brglez, K. Kozminski","doi":"10.1109/EASIC.1990.207905","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207905","url":null,"abstract":"OASIS is a cell-based silicon compiler system that supports rapid implementation of digital Application Specific ICs (ASICs) by taking a high-level language description and producing a layout of a testable IC. The language unifies functional descriptions of finite state machines (FSMs) and decoding logic with structural/algorithmic descriptions of data paths and regular structures such as adders or multipliers. The OASIS system integrates the language compiler with logic synthesis, simulation, verification, testability, and layout tools, providing the necessary control to explore the speed-versus-area tradeoffs. The authors' experience with a language-based design capture system shows a marked increase in productivity when compared to schematic capture. This paper describes the system with its unique features and presents some of the results of using OASIS in designing semicustom ASICs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1998 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128234766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Constraint-driven synthesis from architectures described in ELLA 来自ELLA中描述的架构的约束驱动的综合
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207977
J. Saunders, C. Clee
{"title":"Constraint-driven synthesis from architectures described in ELLA","authors":"J. Saunders, C. Clee","doi":"10.1109/EASIC.1990.207977","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207977","url":null,"abstract":"Demonstrates how the new synthesis tool LOCAM, provided by Praxis Electronic Design, gives system designers, for the first time, an automatic route to silicon from behavioural descriptions of their intended architectures. LOCAM avoids the need for time-consuming, error-prone logic design and raises the design reference level from boolean logic equations to abstract descriptions of architectures. The paper illustrates how the performance of a chosen architecture can be pre-determined both by the nature of the ELLA description and by user-defined constraints imposed on LOCAM.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130855043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An application specific IC for digital signal processing: the floating point pipeline CORDIC processor 用于数字信号处理的专用IC:浮点流水线CORDIC处理器
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207911
A. de Lange, A.J. van der Hoeven, E. Deprettere, P. Dewilde
{"title":"An application specific IC for digital signal processing: the floating point pipeline CORDIC processor","authors":"A. de Lange, A.J. van der Hoeven, E. Deprettere, P. Dewilde","doi":"10.1109/EASIC.1990.207911","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207911","url":null,"abstract":"Describes concepts, design and implementation of a Coordinate Rotation Digital Computer (CORDIC) processor element that can be used in processor arrays for high-speed processing. The processor is intended to achieve maximal throughput m-matrix computations. It is a systolic processor that performs plane rotations in two different coordinate systems.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134527502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The microprocessor support peripheral family and the direct access test methodology 微处理器支持外设系列和直接存取测试方法
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207970
E.M. Aleman
{"title":"The microprocessor support peripheral family and the direct access test methodology","authors":"E.M. Aleman","doi":"10.1109/EASIC.1990.207970","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207970","url":null,"abstract":"Designs using LSI peripherals could have testability problems when peripheral I/O's are embedded within the design. A designer must contend with both lack of circuit knowledge and time when developing production test programs for new LSI ASIC offerings. This paper will introduce Intel's microprocessor support peripheral family and the direct access test scheme (DAT). The DAT was developed to isolate each peripheral and allow all signals to be controllable and observable from the package pins. Isolating peripherals allows the designer to use the standard duct test programs. Each MSPF cell will be discussed and compared with its standard product equivalent. Built-in test modifications and additions to the peripherals will be outlined. Testability rules and guidelines are included.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130071524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated circuit for self-routing data and voice switching 用于自路由数据和语音交换的集成电路
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207974
R. Luijten
{"title":"An integrated circuit for self-routing data and voice switching","authors":"R. Luijten","doi":"10.1109/EASIC.1990.207974","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207974","url":null,"abstract":"This paper describes the development of the architecture and implementation of a self-routing switch-fabric chip which accommodates packetized voice and data traffic. A prototype VLSI chip has been built in a one-micron CMOS standard cell technology. The prototype has 16 input and 4 output ports. Each port supports a data rate of 32 Mb/s. A fabric with 16 input and 16 output ports can be configured from four prototype chips. The fabric routes traffic from any input to any output port. The chip has internal memory for queuing to resolve output port contention, and is designed for use as a building block to construct larger switch fabric sizes.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"33 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120993198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of an integrated programmable neurostimulator 集成可编程神经刺激器的设计
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207917
A. Kachouri, M. Robert, D. Deschacht, N. Lakhoua, D. Auvergne
{"title":"Design of an integrated programmable neurostimulator","authors":"A. Kachouri, M. Robert, D. Deschacht, N. Lakhoua, D. Auvergne","doi":"10.1109/EASIC.1990.207917","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207917","url":null,"abstract":"Presents the design of an integrated neurostimulator, offering to surgeons the facilities to recognize nervous anatomy according to the muscular response obtained, as well as the identification of possible lesions. The system has been implemented with level and duration programmable current sources, offering large range of possibilities. The authors a describe the circuit specification, the architecture of the ASIC designed in a 2 mu m CMOS technology, and present characterization of the prototypes, manufactured by ES2.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122208163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ADS analog digital system, a novel approach to CAD for mixed analog/digital ASICs ADS模拟数字系统是一种新型的模拟/数字混合集成电路的CAD方法
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.208028
C. Caillon, J. Remy, J. M. Sánchez, S. Scotti
{"title":"ADS analog digital system, a novel approach to CAD for mixed analog/digital ASICs","authors":"C. Caillon, J. Remy, J. M. Sánchez, S. Scotti","doi":"10.1109/EASIC.1990.208028","DOIUrl":"https://doi.org/10.1109/EASIC.1990.208028","url":null,"abstract":"The STKM2000 library is really a merged library: a merge between bipolar and CMOS technologies, a merge between analog and digital functions, a merge between CAD and design concepts. This 'merged' library is able to answer to most of system requirements between sensors and actuators, from lower to video frequencies, from 2.7 V to 11 V applications, with the possibility of accurate functions. With the possibility to implement on a same die 10 K gates with all analog functions, STKM2000 opens the door towards the one chip solutions. Its availability on the majority of standard workstations with a user-friendly human interface and design manager allows to everybody to design himself mixed analog/digital applications.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130378713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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