{"title":"Crosspoint element: Elemento de Cruce (EC)","authors":"A. Altadill, I. Carretero, M. Escudero, P. Mateos","doi":"10.1109/EASIC.1990.207930","DOIUrl":null,"url":null,"abstract":"The VLSI integrated circuit \"Elemento de Cruce\" (EC) has been conceived as a multifunction device. The EC has been designed to work as the crosspoint element in a broadband (ATM) asynchronous transfer mode (ATM) switch block, as well as an interfacing device between a microprocessor, a codec or, in general, any data source and the ATM switch network. The EC works at a frequency of 43.75 MHz using a 16 bit parallel data format, giving a throughput of 700 Mbs. The chip is implemented with 13 K CMOS gates, 4 kbits of RAM memory and 25.5 kbits of FIFO memory. The IC is manufactured in 1.25 mu m twin-tub double metal level standard cell CMOS technology and has dimensions of 400 mils*400 mils, with nominal power dissipation of 1.3 W.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] EURO ASIC `90","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EASIC.1990.207930","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The VLSI integrated circuit "Elemento de Cruce" (EC) has been conceived as a multifunction device. The EC has been designed to work as the crosspoint element in a broadband (ATM) asynchronous transfer mode (ATM) switch block, as well as an interfacing device between a microprocessor, a codec or, in general, any data source and the ATM switch network. The EC works at a frequency of 43.75 MHz using a 16 bit parallel data format, giving a throughput of 700 Mbs. The chip is implemented with 13 K CMOS gates, 4 kbits of RAM memory and 25.5 kbits of FIFO memory. The IC is manufactured in 1.25 mu m twin-tub double metal level standard cell CMOS technology and has dimensions of 400 mils*400 mils, with nominal power dissipation of 1.3 W.<>