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[Proceedings] EURO ASIC `90最新文献

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A floating-point systolic array processing element using serial communication 一个使用串行通信的浮点收缩数组处理元件
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207947
T. Davies, D. Al-Khalili, V. Szwarc
{"title":"A floating-point systolic array processing element using serial communication","authors":"T. Davies, D. Al-Khalili, V. Szwarc","doi":"10.1109/EASIC.1990.207947","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207947","url":null,"abstract":"The authors describe the design of a processing element (PE) for systolic array applications. The PE which is configured as a multiplier-accumulator or an inner product step processor, supports most common systolic algorithms in signal processing and matrix arithmetic. Communication with neighbouring PEs is achieved through 18 on-chip serial links, each operating at 50 Mb per second. The 30 K transistor ASIC device is implemented in 2 micron HCMOS gate array technology, packaged in a 48 pin DIP and performs at 10 MFLOPS.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122566778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Thin film transistors modeling and parameters extraction tool 薄膜晶体管建模和参数提取工具
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207984
O. Declerck, J. Bardyn
{"title":"Thin film transistors modeling and parameters extraction tool","authors":"O. Declerck, J. Bardyn","doi":"10.1109/EASIC.1990.207984","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207984","url":null,"abstract":"Presents a parameters extraction tool for transistors modeling activity, which gives way to characterize not only MOS processes but also to check and validate four terminal transistor models such as polysilicon thin film transistors.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"23 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124553881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pegasus-an ASIC implementation of high-performance PROLOG processor pegasus - ASIC实现的高性能PROLOG处理器
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207928
T. Yokota, K. Seo
{"title":"Pegasus-an ASIC implementation of high-performance PROLOG processor","authors":"T. Yokota, K. Seo","doi":"10.1109/EASIC.1990.207928","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207928","url":null,"abstract":"Pegasus is a single chip RISC microprocessor dedicated to the PROLOG language. Although implementing many ideas for the fast execution of PROLOG programs, its datapath and control are still kept very simple in line with RISC design. A prototype chip of Pegasus was fabricated in 1.5 mu m CMOS technology and integrates 80000 transistors in a 9.7 mm square chip area. For quick fabrication and design scalability, the chip was designed by using high-level design tools except for its register file which is a dedicated dual-port RAM with a special copy function. Although the machine cycle time is slower, the prototype chip achieves comparable performance to other dedicated machines.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129103278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A parallel processor ASIC for real time pattern recognition 用于实时模式识别的并行处理器ASIC
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207959
M. Mostafavi, S. Vishin, W. Dettloff
{"title":"A parallel processor ASIC for real time pattern recognition","authors":"M. Mostafavi, S. Vishin, W. Dettloff","doi":"10.1109/EASIC.1990.207959","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207959","url":null,"abstract":"A real time pattern processing ASIC is described. By exploiting a 1 u, 3.3 V DLM CMOS technology, a 10 MHz 250 k transistor chip was designed for machine vision applications requiring recognition of objects in real time. The architecture, design, simulation methodology, and test strategy of the chip is discussed.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123686822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new algorithm for diagnosis-oriented automatic test pattern generation 一种面向诊断的测试模式自动生成算法
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207964
P. Camurati, D. Medina, P. Prinetto, M. Sonza Reorda
{"title":"A new algorithm for diagnosis-oriented automatic test pattern generation","authors":"P. Camurati, D. Medina, P. Prinetto, M. Sonza Reorda","doi":"10.1109/EASIC.1990.207964","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207964","url":null,"abstract":"Production testing does not only aim at detecting faulty devices, but its goals are often to repair the element or to investigate the cause of failure, so as to tune the manufacturing process. Diagnostic testing is thus becoming the object of attention both in industry and academia, thanks also to the increased power of tools like fault simulators, testability analysers, and ATPGs. Diagnostic testing has two aspects: assessing the diagnostic properties of a given test pattern set or generating test patterns having such properties. This paper deals with the latter aspect. An ATPG algorithm, the Delta -algorithm, generating a pattern able to distinguish between two faults, is described and its preliminary results obtained on a set of benchmark circuits are reported.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127699780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Realization of an integrated equalizer for a 16 QAM/140 Mbit/s digital radio link 16qam / 140mbit /s数字无线电链路集成均衡器的实现
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207981
C. Izorce
{"title":"Realization of an integrated equalizer for a 16 QAM/140 Mbit/s digital radio link","authors":"C. Izorce","doi":"10.1109/EASIC.1990.207981","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207981","url":null,"abstract":"This paper is the presentation of an ASIC performing equalization for a new digital radio link using a 16 QAM modulation scheme. The use of equalizers in such equipment is more and more necessary, as modulation patterns are growing more and more complex. In addition, digital implementations of a signal processing are now preferred, rather than having to cope with problems due to analog realizations.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128201381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Standard cell development flow 标准细胞发育流程
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207987
J. Dreesen
{"title":"Standard cell development flow","authors":"J. Dreesen","doi":"10.1109/EASIC.1990.207987","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207987","url":null,"abstract":"Describes the new standard-cell development flow, being used at Philips Components Nijmegen. The new flow will integrate all aspects of developing a standard-cell library into one program, resulting in a dramatic decrease in development effort and providing the user with a quick release of an errorfree library. Quality is maintained by virtue of a built-in quality control tool. A stick-editor will reduce layout efforts to a few minutes per cell.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"62 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132236588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CMOS fast FIR filter CMOS快速FIR滤波器
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207936
M. Cand, P. Duhamel, Zhijian Mou
{"title":"CMOS fast FIR filter","authors":"M. Cand, P. Duhamel, Zhijian Mou","doi":"10.1109/EASIC.1990.207936","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207936","url":null,"abstract":"A cascadable circuit for high speed filtering has been made in a 1.2 mu m CMOS technology. Its structure allows the circuit to perform a 40 taps transversal filter either at 3 MHz alone or up to 50 MHz in a simple cascaded configuration of 16 circuits. The coefficients of the filter are mask programmable. The purpose of this circuit is for satellite communications.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131743708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Verifying ASICs by symbolic simulation 用符号仿真验证asic
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207990
R. Schmid, E. Tidén
{"title":"Verifying ASICs by symbolic simulation","authors":"R. Schmid, E. Tidén","doi":"10.1109/EASIC.1990.207990","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207990","url":null,"abstract":"A new tool which is capable of dealing with digital circuit designs on a functional, or behavioural, level is presented. The tool has been used extensively in a design center for ASICS, and several real-life applications of it are described. The basis of the new tool is formed by efficient algorithms for manipulating Boolean functions and finite-state machines. Among the applications of the tool are automatic formal verification of combinatorial and sequential circuits, reverse engineering, (e.g. generation of state transition tables from circuit designs), rapid prototyping. validation of new CAD tools, verification of hand optimizations of tool-generated circuits and algorithm design.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"137 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133322966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Timing aspects of cell-based ASIC design 基于单元的ASIC设计的时序方面
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207965
H. Youssef, E. Shragowitz
{"title":"Timing aspects of cell-based ASIC design","authors":"H. Youssef, E. Shragowitz","doi":"10.1109/EASIC.1990.207965","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207965","url":null,"abstract":"Increase in the density of integrated circuits and decrease in feature size have altered the nature of timing problems and made timing dependent on the electrical properties of interconnections, their drivers, and their loads. This paper proposes a new methodology for the isolation of the critical paths prior to the physical design step and the development of timing constraints on all the nets, which are consistent with the required performance. These data are used to influence the physical design. Description of the approach is accompanied by applications to real designs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123442900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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