{"title":"ASIC design methods using VHDL","authors":"R. Curtin","doi":"10.1109/EASIC.1990.207933","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207933","url":null,"abstract":"The design of increasingly more complex custom and semicustom integrated circuits has traditionally forced the introduction of new design methodologies. Formal specifications, top-down design, and design-for-test have become standard practices for IC design teams. The adoption of VHDL (VHSIC Hardware Description Language), as an IEEE standard (IEEE-1076), and the recent availability of design automation tools supporting VHDL, has begun yet another wave of change in the ASIC design process. The author investigates the impact of VHDL on the ASIC design team, as well as on the ASIC manufacturer. It is his intention to identify areas which must be investigated by the ASIC community before incorporating VHDL in the design process.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127373615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A MC680x0 compatible coprocessor for binary image processing","authors":"J. Legat, P. De Muelenaere","doi":"10.1109/EASIC.1990.207972","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207972","url":null,"abstract":"A new ASIC coprocessor has been designed binary image processing applications. This dedicated IC has been fabricated in a 1.5 micron CMOS technology and contains 50000 gates. An important feature is that the chip is developed to be fully compatible with the Motorola MC680x0 family of processors. It works in coprocessor or peripheral mode on a 8-, 16- or a 32-bit bus.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129785626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PLAYL: a general-purpose data path assembler","authors":"N.H. Nam, D. Laurent","doi":"10.1109/EASIC.1990.207951","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207951","url":null,"abstract":"This paper describes PLAYL, a data path assembler and methodology that provides an efficient way of mapping a procedural specification into a flexible layout style. New routing techniques were developed in order to handle the specific constraints of a data path. This tool was developed not only with purpose of generating data path layouts but also with the ability to provide for multiple architectures within one generator framework. PLAYL is being used to design the data paths for the VLSI circuits which compose the CPUs of DPS7 and DPS8 mainframe computers.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126479634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Real time graphics processor","authors":"P. Geneste, D. Auger","doi":"10.1109/EASIC.1990.207961","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207961","url":null,"abstract":"A real-time fully programmable graphics processor, previously implemented with several custom and semi-custom ASICs, has been shrunk into a single 1 mu m CMOS chip called Monochip Graphic Processor (MGP). Development of previous chip set started in 1979 to mid 1986, therefore different technologies and methodologies were used throughout the designs. Main challenge was to cope with almost 10 year old designs, providing fully functional compatibility especially at software level for airborne software certification reasons.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133125837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application of digital CMOS ASICs in a medical diagnostic imaging design","authors":"R. Fehr","doi":"10.1109/EASIC.1990.207960","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207960","url":null,"abstract":"A new line of medical diagnostic imaging instruments was designed using application-specific integration as a key technology. An outstanding price-performance ratio can be achieved using a system integration approach. Development- and production-costs are discussed, given the case of a low volume/high complexity product.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129888170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Autodiagnosis speeds turn around time","authors":"P. Ovington","doi":"10.1109/EASIC.1990.207969","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207969","url":null,"abstract":"As gate arrays become more complex, the test vector generations effort increases in an alarming fashion. This problem has existed for some time, and there have been many attempts at devising a solution. This paper describes Hitachi's autodiagnosis concept, which has proved to be enormously successful. Gate array development has now reached a stage of some maturity, and very high densities are being offered by some manufactures. Although, these devices are freely available there still seems some reluctance on the part of potential users to seize the opportunity of designing such devices into their systems. The reason is well understood. As the ratio of gate density of I/O pins increases rapidly, the logic in the core of the array becomes difficult to test. Basically, as the logic becomes more inaccessible from the pins, the controllability and observability fall rapidly.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126255567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The synchronism checker","authors":"D. Motshagen, J. Galletero","doi":"10.1109/EASIC.1990.207907","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207907","url":null,"abstract":"Presents an example of the integration of an industrial circuit. The design of an ASIC is different from a design for a PCB. The different choice of components on one hand, and reliability and testability on the other, demand special considerations to be taken into account when a PCB circuit is transformed into an ASIC. Several of these will be discussed. A semi-custom circuit is presented which controls a switch in the high voltage networks of a power system. SOLO 1200 design tools and ES2 technology are used. The circuit is designed for GEPCE in Bilbao, Spain. The design is based on a patented PCB circuit. Some major changes are necessary to facilitate the integration. The circuit is made completely synchronous. Scan-paths are introduced to obtain a good testability.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125443949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Logic synthesis","authors":"P. Hollingworth","doi":"10.1109/EASIC.1990.207949","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207949","url":null,"abstract":"An average engineer working on an ASIC project designs between 200 ad 500 gates per week. With design complexity increasing and time-to-market becoming more critical, considerable attention is being focussed on how to improve productivity. Synthesis offers a great deal of promise. In this paper LSI Logic explain their approach to logic synthesis, both in terms of their inhouse tools and the ability to support third party routes. The Logic Expression Synthesizer (LES) and Logic Block Synthesizer (LBS) tools are discussed in detail. LBS can synthesize a variety of modules, for example carry-select adders, gray code counters and fall-through FIFOs: while LES is capable of outputting an optimised netlist from both low and high level forms of input, including FSM and RTL formats. Finally, future approaches to synthesis are discussed, including behavioural synthesis from VHDL.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128703036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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