{"title":"PLAYL:一个通用的数据路径汇编程序","authors":"N.H. Nam, D. Laurent","doi":"10.1109/EASIC.1990.207951","DOIUrl":null,"url":null,"abstract":"This paper describes PLAYL, a data path assembler and methodology that provides an efficient way of mapping a procedural specification into a flexible layout style. New routing techniques were developed in order to handle the specific constraints of a data path. This tool was developed not only with purpose of generating data path layouts but also with the ability to provide for multiple architectures within one generator framework. PLAYL is being used to design the data paths for the VLSI circuits which compose the CPUs of DPS7 and DPS8 mainframe computers.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"PLAYL: a general-purpose data path assembler\",\"authors\":\"N.H. Nam, D. Laurent\",\"doi\":\"10.1109/EASIC.1990.207951\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes PLAYL, a data path assembler and methodology that provides an efficient way of mapping a procedural specification into a flexible layout style. New routing techniques were developed in order to handle the specific constraints of a data path. This tool was developed not only with purpose of generating data path layouts but also with the ability to provide for multiple architectures within one generator framework. PLAYL is being used to design the data paths for the VLSI circuits which compose the CPUs of DPS7 and DPS8 mainframe computers.<<ETX>>\",\"PeriodicalId\":205695,\"journal\":{\"name\":\"[Proceedings] EURO ASIC `90\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] EURO ASIC `90\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EASIC.1990.207951\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] EURO ASIC `90","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EASIC.1990.207951","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes PLAYL, a data path assembler and methodology that provides an efficient way of mapping a procedural specification into a flexible layout style. New routing techniques were developed in order to handle the specific constraints of a data path. This tool was developed not only with purpose of generating data path layouts but also with the ability to provide for multiple architectures within one generator framework. PLAYL is being used to design the data paths for the VLSI circuits which compose the CPUs of DPS7 and DPS8 mainframe computers.<>