{"title":"Autodiagnosis speeds turn around time","authors":"P. Ovington","doi":"10.1109/EASIC.1990.207969","DOIUrl":null,"url":null,"abstract":"As gate arrays become more complex, the test vector generations effort increases in an alarming fashion. This problem has existed for some time, and there have been many attempts at devising a solution. This paper describes Hitachi's autodiagnosis concept, which has proved to be enormously successful. Gate array development has now reached a stage of some maturity, and very high densities are being offered by some manufactures. Although, these devices are freely available there still seems some reluctance on the part of potential users to seize the opportunity of designing such devices into their systems. The reason is well understood. As the ratio of gate density of I/O pins increases rapidly, the logic in the core of the array becomes difficult to test. Basically, as the logic becomes more inaccessible from the pins, the controllability and observability fall rapidly.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] EURO ASIC `90","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EASIC.1990.207969","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
As gate arrays become more complex, the test vector generations effort increases in an alarming fashion. This problem has existed for some time, and there have been many attempts at devising a solution. This paper describes Hitachi's autodiagnosis concept, which has proved to be enormously successful. Gate array development has now reached a stage of some maturity, and very high densities are being offered by some manufactures. Although, these devices are freely available there still seems some reluctance on the part of potential users to seize the opportunity of designing such devices into their systems. The reason is well understood. As the ratio of gate density of I/O pins increases rapidly, the logic in the core of the array becomes difficult to test. Basically, as the logic becomes more inaccessible from the pins, the controllability and observability fall rapidly.<>