Timing aspects of cell-based ASIC design

Increase in the density of integrated circuits and decrease in feature size have altered the nature of timing problems and made timing dependent on the electrical properties of interconnections, their drivers, and their loads. This paper proposes a new methodology for the isolation of the critical paths prior to the physical design step and the development of timing constraints on all the nets, which are consistent with the required performance. These data are used to influence the physical design. Description of the approach is accompanied by applications to real designs.<>