{"title":"A mixed analog/digital ASIC for real time spectrum analysis","authors":"J. Bardyn, A. Kaiser, P. Masquelier","doi":"10.1109/EASIC.1990.207937","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207937","url":null,"abstract":"A circuit dedicated to real time spectrum analysis has been implemented in a 3 microns CMOS technology. Power spectral density is measured with an error of less than 1% in a frequency range from 100 Hz to 50 kHz. Specific dynamic offset reduction techniques have been developed for the full custom analog part. Real time programming is possible through the standard cell digital part.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129698708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Genoe, W. Pioegaerts, L. Claesen, H. de Man, C. Tricarico, R. Delpretti, D. Dauw
{"title":"An ASIC for die-sinking spark erosion simulations","authors":"M. Genoe, W. Pioegaerts, L. Claesen, H. de Man, C. Tricarico, R. Delpretti, D. Dauw","doi":"10.1109/EASIC.1990.207946","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207946","url":null,"abstract":"Electrical discharge machining (EMD) simulation has always been considered as a very hard problem, for reasons that such simulations are extremely computation intensive. However, the authors present a wide range of implementations for the die-sinking spark erosion process, which prove that EDM simulations are today executable in an acceptable time. All the implementations proposed here are designed in a fully automatic way, using the Cathedral Silicon Compilers System developed at IMEC-Heverlee. The results are compared with similar implementations on a TMS320 domain specific commercial signal processor. From the viewpoint of EDM-users, these simulations are very useful because the final results of this kind of thermo-electrical process are in no way predictable.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ARINC 429 data concentrator","authors":"C. Pitot, C.C. Vaubois, M. Prost, L. Pot","doi":"10.1109/EASIC.1990.207912","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207912","url":null,"abstract":"The Airbus A320 program introduced the 'fly by wire' concept in commercial transport airplanes. Within this plane for flight management and guidance systems integration, a communication problem had risen, because of the great number of ARINC 429 lines which a computer had to listen to in order to perform its function. This constraint had led to the need for and the design of very compact and powerful ARINC 429 reception units, all of them based on a common architecture using extensively a gate-array-based ASIC called 'SR8A'. This paper presents the hardware architectural concept of ARINC 429 Data concentrators which are used by SEXTANT Avionique Company for both the A320 and A340/330 commercial transport airplanes. In respect to these guidelines, a family of inter-compatible circuits were designed in order to fit a very wide ARINC 429 application panel. Then, the authors present their features and the methodology used during their design.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127468235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Extension of the MOSART circuit simulator to the analysis of BiCMOS circuits","authors":"A. Vachoux, N. Anwar","doi":"10.1109/EASIC.1990.207967","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207967","url":null,"abstract":"MOSART is a MOS-VLSI time-domain simulator which implements the waveform relaxation analysis technique. The extension of the simulator to mixed bipolar-MOS circuits presented in this paper makes use of the particular structure of such circuits to decompose them without 'breaking' the bipolar transistors. A modified decomposition algorithm along with some application examples are also presented.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"16 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132899874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and test of a complex telecom ASIC: the NIARL","authors":"F.C. Torre, J.P. Melian","doi":"10.1109/EASIC.1990.207980","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207980","url":null,"abstract":"Describes several aspects of a new integrated circuit, the NIARL, which can perform packet switching between two statistical links at 2.048 MHz and circuit switching between three PCM links, one internal to a module (minimum part of the system) and two others from the local network, also at 2.048 MHz.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132902254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A routing concept for large sea-of-gates designs","authors":"M. Bartholomeus, W. Weisenseel","doi":"10.1109/EASIC.1990.207944","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207944","url":null,"abstract":"Sea-of-gates (SoG) is becoming a very important design style for ASICs. Due to a larger flexibility in placement and routing, SoG can achieve higher densities and gate count than conventional gate arrays. Ion this paper the authors describe a routing environment and a routing methodology utilizing all features of this new design style, aiming to automatically complete a large design with high gate utilization, zero uncompleted routing connections with reasonable CPU-resources. In general, this problem cannot be solved with a single algorithm. Rather, a sequence of algorithms which are hierarchical and/or optimized to perform specialized tasks are used.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130881715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Built-in self-test for generated blocks in an ASIC environment","authors":"V. Bruchner, A. Achuetz","doi":"10.1109/EASIC.1990.207962","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207962","url":null,"abstract":"Techniques for Built-in Self-Test of RAMs embedded within ASIC's are presented. The test algorithm (sequence) has been laid out with emphasis on high fault coverage and low silicon overhead. It supports existing RAM generator tool and allows for generating a wide spectrum of possible configurations. The BIST circuit itself is a soft-macro built from standard library elements. The schematic will be generated automatically on design station according to user specifications. User friendliness was a top goal for the development.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114458505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic synthesis of mu programmed controllers","authors":"L. Gerbaux, G. Saucier","doi":"10.1109/EASIC.1990.207927","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207927","url":null,"abstract":"The authors present an optimal synthesis method of programmed controllers. Starting from a control flowchart, a synthesis tool generates automatically the content of the ROM and a standard cell implementation of the mu sequencer. An optimization effort focuses on the ROM block. It is based on an optimized assignment of states to ROM addresses using embedding technique in the hypercube.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114474176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Jay, M. Crastes de Paulet, M. Karam, G. Saucier
{"title":"Hierarchical test generation for data path","authors":"C. Jay, M. Crastes de Paulet, M. Karam, G. Saucier","doi":"10.1109/EASIC.1990.207963","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207963","url":null,"abstract":"A method of hierarchical test generation for data path is proposed. The test patterns are generated for the basic blocks of a classical data path library. These test patterns are propagated to the inputs and to the outputs of the data path by two methods. The first one, practically implemented, enumerates backpropagation paths based on structural considerations, selects one and then performs consistency for real local test patterns. The second one works directly on symbolic values and uses immediately the back and forward propagation paths. Both methods take advantage of the existence of transparent blocks.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117136278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ASAP: a portable program for the symbolic analysis of analog integrated circuits","authors":"F. Fernández, Á. Rodríguez-Vázquez, J. L. Huertas","doi":"10.1109/EASIC.1990.207914","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207914","url":null,"abstract":"A new and efficient symbolic analyzer for analog integrated circuits, ASAP (Analog Symbolic Analysis Program), is presented. ASAP provides symbolic expressions for all types of AC transfer and driving-point characteristics of analog integrated circuits. The resulting expressions can be automatically simplified, which makes them useful for circuit synthesis. The main features of the program are described as well as some illustrative examples showing the usefulness and efficiency of the program.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115489550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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