Built-in self-test for generated blocks in an ASIC environment

Abstract

Techniques for Built-in Self-Test of RAMs embedded within ASIC's are presented. The test algorithm (sequence) has been laid out with emphasis on high fault coverage and low silicon overhead. It supports existing RAM generator tool and allows for generating a wide spectrum of possible configurations. The BIST circuit itself is a soft-macro built from standard library elements. The schematic will be generated automatically on design station according to user specifications. User friendliness was a top goal for the development.<>