J. Madre, O. Coudert, M. Currat, A. Debreil, C. Berthet
{"title":"The formal verification chain at BULL","authors":"J. Madre, O. Coudert, M. Currat, A. Debreil, C. Berthet","doi":"10.1109/EASIC.1990.207991","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207991","url":null,"abstract":"Presents the chain of tools developed at BULL for the verification of circuit designs. For several years, BULL has been a leading site in the field of formal verification of hardware. Until now, the main concern of BULL was in the validation of the VLSI circuits of its mainframe CPUs. The effort is currently extended to board components such as PLDs and ASICs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123410047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analog circuit synthesis with simplified knowledge acquisition and fast transistor sizing","authors":"M. Alger","doi":"10.1109/EASIC.1990.207921","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207921","url":null,"abstract":"Presents a system for analog CMOS circuit synthesis. It tries to overcome shortcomings of the rule based expert system approach at the stage of the circuit composition and provides sized netlists without simulation based optimization being necessary. A functional description of the required circuit is used to compose an application-appropriate schematic out of a set of parameterizable subcells. Transistor sizing is done with a table model which accurately relates small-signal transistor parameters to widths and lengths. The small-signal parameters are found from circuit specification using first order model equations. The table may be constructed through measurements or with presimulated values. The latter allows one to take parasitic layout effects into account in advance. A design example is presented.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121712789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A highly flexible dual-port-RAM compiler","authors":"F. Muehlegg, A. Schuetz","doi":"10.1109/EASIC.1990.207954","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207954","url":null,"abstract":"A highly flexible dual-port-RAM compiler will be presented. A very robust design flow facilitates the integration of specially tailored dual-port-RAMs into ASIC designs even by non IC literate users. Generated modules contain all the necessary representations for use in the design system together with a proprietary standard cell library. The major application areas for dual-port-RAMs are cache memories, FIFOs, interface buffers, register files and video RAMs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129282356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated schematic capture with the USC51 embedded microcontroller","authors":"E.M. Aleman, J. Couleur","doi":"10.1109/EASIC.1990.207989","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207989","url":null,"abstract":"The UCS51 product family was implemented to allow ASIC proliferations of the 80C51 microcontroller. The many configuration options available made it apparent that a tool was needed to aid designers during the core configuration phase of the schematic capture process. This tool is called the UCS51 Design Entry Tool (DET). The DET offers built-in design rule checking, and all connections are guaranteed to be correct by construction. The DET is discussed step by step, menu by menu. Options discussed include: adding peripherals; deleting peripherals; customizing interconnections; saving core configuration; and creating a schematic. Use of the DET to generate partial assembly code for test pattern development is included.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131664113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-level synthesis on programmable devices in the ASYL system","authors":"G. Saucier, P. Sicard, L. Bouchet","doi":"10.1109/EASIC.1990.207924","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207924","url":null,"abstract":"Starting from Boolean equations or, at a higher level, from a control flowchart, the automatic synthesis tool presented here, looks for an optimized mapping on a network of programmable modules. For PALs, the output will be a network of PALs and a netlist ready for a Jedec fusemap; for the Xilinx PGAs the system delivers a network of Xilinx blocks and a netlist. For the last target a place and route phase is necessary.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133317745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A mixed digital-analog simulation and test environment","authors":"R. Lanoo","doi":"10.1109/EASIC.1990.208029","DOIUrl":"https://doi.org/10.1109/EASIC.1990.208029","url":null,"abstract":"A mixed digital-analog simulation and test environment, MIXTEST, has been developed, bridging the gap between a design and test department by automatic translation of the simulation results from the mixed digital-analog simulator, MIXSIM, into a mixed test program. This system truly allows design for testability on mixed digital-analog circuits, by using a test machine database containing all restrictions of the supported test equipment, during the design phase.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115448115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analog-digital integrated test concerns","authors":"N. Crawley","doi":"10.1109/EASIC.1990.207957","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207957","url":null,"abstract":"Considers the practical test issues concerned with design verification of prototype mixed signal components. Mixed signal testing is treated as an extension to familiar digital test techniques.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115717500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Beller, M. Beunder, V. Dudek, B. Hoefflinger, J. Kernhof, M. Schau
{"title":"A semi-custom pad library","authors":"W. Beller, M. Beunder, V. Dudek, B. Hoefflinger, J. Kernhof, M. Schau","doi":"10.1109/EASIC.1990.207988","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207988","url":null,"abstract":"Describes the design of a pad library for a semi-custom array family. It discusses the requirements defined by the application environment of semi-custom arrays. These requirements are subsequently translated into components and their respective characteristics. Three types of pads are distinguished: (1) power pads; (2) input, output, bi-directional and tri-state pads; and (3) special pads. The design of the pad master and its respective personalizations are described, together with their physical characteristics. Measurements of important characteristics are described, including ESD measurements and hot-electron effects.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126572381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The development of a cryptographic device","authors":"J. B. Roubos, R. Pieterse","doi":"10.1109/EASIC.1990.207975","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207975","url":null,"abstract":"Gives an overview of the development of a cryptographic system at the Research Laboratory of the Royal Dutch PTT. Part of this system is a (cryptographic) ASIC. The authors of this paper give an overview of the development process of this ASIC. It was the first full custom development of an ASIC inside the laboratory. They found that it involved many new steps, related to the technical AND to the management field. Some guidelines on ASIC worlds are given.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124936604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Boarin, G. Chiappano, F. Maloberti, S. Napolitano, M. Porta
{"title":"VLSI implementation of the metering signal generator for switching system analog terminations","authors":"G. Boarin, G. Chiappano, F. Maloberti, S. Napolitano, M. Porta","doi":"10.1109/EASIC.1990.207983","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207983","url":null,"abstract":"Describes a mixed analog-digital integrated circuit to be employed in a Central Exchange Switching System. This generates a proper shaped telephone metering pulse, according to the actual international standards, and sends it to eight subscribers. It has been designed with a cell-based approach and implemented with a 3 mu m double poly single metal CMOS technology. 80% of the circuit uses digital and analog cells, while 20% has been specifically designed down to a transistor level. In order to reduce the power consumption two different supplies was used.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123671336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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