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[Proceedings] EURO ASIC `90最新文献

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Dedicated processor for partial differential equation solver 偏微分方程求解专用处理器
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207948
F. Theodorou, F. Gaffiot, B. Boutherin, R. Menezia, M. Le Helley
{"title":"Dedicated processor for partial differential equation solver","authors":"F. Theodorou, F. Gaffiot, B. Boutherin, R. Menezia, M. Le Helley","doi":"10.1109/EASIC.1990.207948","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207948","url":null,"abstract":"A hardware solver for Delta Psi =f( Psi ), by the finite-difference method in 3D is presented. The general architecture is given: several identical processors run in a parallel mode in a PC-type environment. Each processor is a specific circuit (ASIC). The arithmetic unit has been integrated in a CMOS 2 mu m technology. Using this circuit to simulate potential distribution in silicon devices shows a drastic reduction of the computation time, 1.7 mu s per discretization node against 900 mu s by a software approach.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122162134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Vantage Spreadsheet-a new approach to VHDL simulation Vantage电子表格- VHDL仿真的新方法
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207935
A. F. Page
{"title":"Vantage Spreadsheet-a new approach to VHDL simulation","authors":"A. F. Page","doi":"10.1109/EASIC.1990.207935","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207935","url":null,"abstract":"The author describes Vantage Spreadsheet, a simulation environment specifically designed for use with VHDL (VHSIC hardware description language). The basic constructs of the language are described, together with the method by which they are integrated into the simulation environment. Further descriptions of particular features of the product are given, including real time schematic simulation.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123244997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI area estimation tolerances-shape function generation vs. floorplanning VLSI面积估计公差-形状函数生成与平面规划
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207940
G. Zimmermann
{"title":"VLSI area estimation tolerances-shape function generation vs. floorplanning","authors":"G. Zimmermann","doi":"10.1109/EASIC.1990.207940","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207940","url":null,"abstract":"Area estimation is an important task during the planning of VLSI systems. Several methods have been proposed. But how can one determine the reliability of an estimate? Can an estimate be 100% correct? The answer is no because the design process is not fully predictable. The predictability is an upper limit for the reliability of estimates. Reliability and predictability are defined and examples given. Two very interesting conclusions are drawn: a good estimate of the area of the \"best\" layout can serve as a termination criterion for design iterations and a good estimate can be more reliable than a prototype layout without iterations.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116523400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A neuron processor for neural networks on silicon 用于硅基神经网络的神经元处理器
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207945
J. Ouali, G. Saucier
{"title":"A neuron processor for neural networks on silicon","authors":"J. Ouali, G. Saucier","doi":"10.1109/EASIC.1990.207945","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207945","url":null,"abstract":"A neuron processor has been designed and implemented on silicon in a 1.5 mu m CMOS technology. It implements a relaxation algorithm with 8 bits precision for the state and the coefficients, and a sigmoidal activation function. It is the building block of a distributed synchronous architecture in which data circulate through shifting techniques.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A test vehicle for monitoring and improvement of CMOS reliability performance 一种监测和改进CMOS可靠性性能的试验车
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207986
G. Remmerie
{"title":"A test vehicle for monitoring and improvement of CMOS reliability performance","authors":"G. Remmerie","doi":"10.1109/EASIC.1990.207986","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207986","url":null,"abstract":"Monitoring reliability performance through accelerated testing on products is at least incomplete and failure analysis is difficult. Device level reliability stress tests are an attractive complement, and offer a wider range of overstresses, a clearer relationship between stress and failure, and reduced stress times. A 2.0 micron CMOS testchip has been built, containing stress patterns for interconnect, dielectrics, diffusions and transistors. A set of stress conditions has been designed, and data handling software has been developed to analyse parameter shifts due to ageing and assembly. The system is used for monitoring and for evaluation of process changes.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132345798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An ASIC controller for the TMS 320, 2-generation digital signal processor tms320的ASIC控制器，2代数字信号处理器
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207939
G. Creanza, O. Ventrella, G. Colangeli, E. Subiaco
{"title":"An ASIC controller for the TMS 320, 2-generation digital signal processor","authors":"G. Creanza, O. Ventrella, G. Colangeli, E. Subiaco","doi":"10.1109/EASIC.1990.207939","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207939","url":null,"abstract":"The authors deal with an ASIC that integrates all the glue logic that allows one or more DSPs, organized in a multiprocessor, linear array system, to communicate with their memories, with a host processor and among themselves. This circuit has been developed as a gate array in the ALCATEL FACE research center with the collaboration of TECNOPOLIS CSATA.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"12 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115027284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Definition of timing models for compiler-driven logic simulation 编译器驱动逻辑仿真的时序模型定义
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207966
W. Hahn, A. Hagerer, M. Eisenhut
{"title":"Definition of timing models for compiler-driven logic simulation","authors":"W. Hahn, A. Hagerer, M. Eisenhut","doi":"10.1109/EASIC.1990.207966","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207966","url":null,"abstract":"The Munich Simulation Engine accelerates compiler-driven simulation and is able to exploit a design's parallelism without restrictions. Advocates of table-driven simulation-engines, however, claim that concerning timing simulation the advantage of compiler-driven simulation engines only exists for zero-delay and, maybe, unit-delay simulation. Based on experience with an operational model of the Munich Simulation Computer, it is shown how to define all types of timing models for compilers-driven simulation and to discuss how far the performance potential of the Munich Simulation Computer is affected when timing models are coded and executed by means of event-flow graphs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"17 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126094964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A flexible gate array RAM compiler with full design tool integration 一个灵活的门阵列RAM编译器与完整的设计工具集成
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207953
R. L. Steinweg, M. Zampaglione, P. Lin
{"title":"A flexible gate array RAM compiler with full design tool integration","authors":"R. L. Steinweg, M. Zampaglione, P. Lin","doi":"10.1109/EASIC.1990.207953","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207953","url":null,"abstract":"Describes a RAM compiler for gate arrays that is well-integrated into the user design tools. The compiler supports variable aspect ratio, with high-level specification, for flexibility in floorplanning. The various hardware and software features and implementation of the compiler are described, with emphasis on the variable aspect ratio. The user design flow is also described, to show how the compiler fits into the design tools.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127811758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Integrated programmable operational amplifiers with improved characteristics 具有改进特性的集成可编程运算放大器
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207913
S. Michael, R. Cristi
{"title":"Integrated programmable operational amplifiers with improved characteristics","authors":"S. Michael, R. Cristi","doi":"10.1109/EASIC.1990.207913","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207913","url":null,"abstract":"A semi-custom integrated circuit featuring digitally programmable operational amplifiers is presented. The OP AMPs realized are based on the composite OP AMPs, previously introduced by the authors and known for their extended bandwidth and reduced active and passive sensitivities. For proof of concept, a small chip was manufactured using the Ferranti Interdesign's CMOS Monochip prototype. A 136 by 185 mils chip containing 200 transistors, four capacitors, and 10 resistors was constructed in a 24 pin package. Experimental results of the prototype chip verified the design concept that was demonstrated theoretically and using SPICE simulation. The results clearly demonstrate the enhanced characteristics of these family of composite OP AMPs when utilized in different applications.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121682066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of an analog I/O ASIC for baseband conversion in digital mobile radio applications 用于数字移动无线电应用中基带转换的模拟I/O ASIC的设计
[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI: 10.1109/EASIC.1990.207919
H. Tucholski, P. Weeks, J. Morrissey, P. O'Connor
{"title":"Design of an analog I/O ASIC for baseband conversion in digital mobile radio applications","authors":"H. Tucholski, P. Weeks, J. Morrissey, P. O'Connor","doi":"10.1109/EASIC.1990.207919","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207919","url":null,"abstract":"The design is discussed. The part is a complete input/output device with a single 5 V supply. As it is necessary for mobile systems to use the lowest possible power, the device has independent power down modes for both the transmit and receive sections of the chip. The part is housed in a space efficient 44 pin PQFP.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"62 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131663205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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