The formal verification chain at BULL

[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI:10.1109/EASIC.1990.207991

J. Madre, O. Coudert, M. Currat, A. Debreil, C. Berthet

引用次数: 5

Abstract

Presents the chain of tools developed at BULL for the verification of circuit designs. For several years, BULL has been a leading site in the field of formal verification of hardware. Until now, the main concern of BULL was in the validation of the VLSI circuits of its mainframe CPUs. The effort is currently extended to board components such as PLDs and ASICs.<>

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BULL的正式验证链

介绍了在BULL开发的用于验证电路设计的工具链。几年来，BULL一直是硬件正式验证领域的领先站点。到目前为止，BULL主要关注的是其大型主机cpu的VLSI电路的验证。目前，这项工作已扩展到电路板组件，如pld和asic。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

[Proceedings] EURO ASIC `90

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