{"title":"一个高度灵活的双端口ram编译器","authors":"F. Muehlegg, A. Schuetz","doi":"10.1109/EASIC.1990.207954","DOIUrl":null,"url":null,"abstract":"A highly flexible dual-port-RAM compiler will be presented. A very robust design flow facilitates the integration of specially tailored dual-port-RAMs into ASIC designs even by non IC literate users. Generated modules contain all the necessary representations for use in the design system together with a proprietary standard cell library. The major application areas for dual-port-RAMs are cache memories, FIFOs, interface buffers, register files and video RAMs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A highly flexible dual-port-RAM compiler\",\"authors\":\"F. Muehlegg, A. Schuetz\",\"doi\":\"10.1109/EASIC.1990.207954\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A highly flexible dual-port-RAM compiler will be presented. A very robust design flow facilitates the integration of specially tailored dual-port-RAMs into ASIC designs even by non IC literate users. Generated modules contain all the necessary representations for use in the design system together with a proprietary standard cell library. The major application areas for dual-port-RAMs are cache memories, FIFOs, interface buffers, register files and video RAMs.<<ETX>>\",\"PeriodicalId\":205695,\"journal\":{\"name\":\"[Proceedings] EURO ASIC `90\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] EURO ASIC `90\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EASIC.1990.207954\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] EURO ASIC `90","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EASIC.1990.207954","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A highly flexible dual-port-RAM compiler will be presented. A very robust design flow facilitates the integration of specially tailored dual-port-RAMs into ASIC designs even by non IC literate users. Generated modules contain all the necessary representations for use in the design system together with a proprietary standard cell library. The major application areas for dual-port-RAMs are cache memories, FIFOs, interface buffers, register files and video RAMs.<>