ASYL系统中可编程器件的多级合成

[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI:10.1109/EASIC.1990.207924

G. Saucier, P. Sicard, L. Bouchet

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引用次数: 11

摘要

从布尔方程开始，或者在更高的层次上，从控制流程图开始，这里介绍的自动合成工具在可编程模块网络上寻找优化映射。对于pal，输出将是一个pal网络和一个准备用于Jedec融合图的网络列表;对于Xilinx PGAs，系统提供Xilinx模块网络和网络列表。对于最后一个目标，一个位置和路线阶段是必要的

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Multi-level synthesis on programmable devices in the ASYL system

Starting from Boolean equations or, at a higher level, from a control flowchart, the automatic synthesis tool presented here, looks for an optimized mapping on a network of programmable modules. For PALs, the output will be a network of PALs and a netlist ready for a Jedec fusemap; for the Xilinx PGAs the system delivers a network of Xilinx blocks and a netlist. For the last target a place and route phase is necessary.<>

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[Proceedings] EURO ASIC `90

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