Multi-level synthesis on programmable devices in the ASYL system

Abstract

Starting from Boolean equations or, at a higher level, from a control flowchart, the automatic synthesis tool presented here, looks for an optimized mapping on a network of programmable modules. For PALs, the output will be a network of PALs and a netlist ready for a Jedec fusemap; for the Xilinx PGAs the system delivers a network of Xilinx blocks and a netlist. For the last target a place and route phase is necessary.<>