内置自检生成块在ASIC环境

[Proceedings] EURO ASIC `90 Pub Date : 1990-05-29 DOI:10.1109/EASIC.1990.207962

V. Bruchner, A. Achuetz

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引用次数: 1

摘要

介绍了ASIC内嵌ram的内建自检技术。测试算法(序列)以高故障覆盖率和低硅开销为重点。它支持现有的RAM生成器工具，并允许生成广泛的可能配置。BIST电路本身是一个由标准库元素构建的软宏。根据用户要求，在设计站自动生成原理图。用户友好是开发的首要目标。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Built-in self-test for generated blocks in an ASIC environment

Techniques for Built-in Self-Test of RAMs embedded within ASIC's are presented. The test algorithm (sequence) has been laid out with emphasis on high fault coverage and low silicon overhead. It supports existing RAM generator tool and allows for generating a wide spectrum of possible configurations. The BIST circuit itself is a soft-macro built from standard library elements. The schematic will be generated automatically on design station according to user specifications. User friendliness was a top goal for the development.<>

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[Proceedings] EURO ASIC `90

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