{"title":"Design and test of a complex telecom ASIC: the NIARL","authors":"F.C. Torre, J.P. Melian","doi":"10.1109/EASIC.1990.207980","DOIUrl":null,"url":null,"abstract":"Describes several aspects of a new integrated circuit, the NIARL, which can perform packet switching between two statistical links at 2.048 MHz and circuit switching between three PCM links, one internal to a module (minimum part of the system) and two others from the local network, also at 2.048 MHz.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"105 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] EURO ASIC `90","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EASIC.1990.207980","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Describes several aspects of a new integrated circuit, the NIARL, which can perform packet switching between two statistical links at 2.048 MHz and circuit switching between three PCM links, one internal to a module (minimum part of the system) and two others from the local network, also at 2.048 MHz.<>